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Issue #1296

SystemVerilog logic array inside struct should warn on bad index

Added by Sergi Granell over 1 year ago. Updated 11 months ago.

Status:
NoFixNeeded
Priority:
Normal
Assignee:
-
Category:
Lint
% Done:

0%


Description

It looks like when you have a logic array inside a struct, and you try to access a bit of that field directly, they indexing of the bits always start at 0 no matter the offset of the logic array.

module our();
    typedef struct packed {
        logic [31:20] imm;
        logic [19:15] rs1;
        logic [14:12] funct3;
        logic [11:7] rd;
        logic [6:0] opcode;
    } instruction_itype_t;

    /*
     * The bit 31, same as instr.imm[11] will be 1.
     */
    instruction_itype_t instr = 32'ha0008093; /* addi x1, x1, -1536 # aa00 */

    logic [11:0] imm;
    assign imm = instr.imm;

    initial begin
        $display("instr: 0x%X\n", instr);

        $display("instr.imm: %b (0x%X)", instr.imm, instr.imm);
        $display("imm:       %b (0x%X)\n", imm, imm);

        /*
         * Should print 1 and not 0!!
         */
        $display("instr.imm[11]: %d <-- should be 1 !!", instr.imm[11]);
        /*
         * This prints 1 as expected.
         */
        $display("imm[11]:       %d\n", imm[11]);

        /*
         * Why is this working? That imm has 12 bits!
         */
        $display("instr.imm[31]: %d", instr.imm[31]);
        $finish;
    end
endmodule

History

#1 Updated by Wilson Snyder over 1 year ago

  • Subject changed from SystemVerilog logic array inside struct: wrong indexing to SystemVerilog logic array inside struct should warn on bad index
  • Category set to Lint
  • Status changed from New to Feature

No.

logic [31:20] imm;
$display("instr.imm[11]: %d <-- should be 1 !!", instr.imm[11]);

Imm is declared as [31:20] so reading bit 11 is illegal. Verilator decides that it will put a zero there to make faster code, but really it's an "X".

Indeed when I try this code on another simulator it gives an error message right on your "should be" extract.

Of course when you then assign it to a "logic [11:0]" you've reestablished the LSB/MSB range so the code is now ok, and as expected you get the right result.

So, Verilator is compliant run-time wise. However it really should give you a warning to point out the code is nonsensical, which is what I'll re-purpose this bug as a request to add.

#2 Updated by Sergi Granell over 1 year ago

Wilson Snyder wrote:

No.

logic [31:20] imm; $display("instr.imm11: %d <-- should be 1 !!", instr.imm11);

Imm is declared as [31:20] so reading bit 11 is illegal. Verilator decides that it will put a zero there to make faster code, but really it's an "X".

Indeed when I try this code on another simulator it gives an error message right on your "should be" extract.

Of course when you then assign it to a "logic [11:0]" you've reestablished the LSB/MSB range so the code is now ok, and as expected you get the right result.

So, Verilator is compliant run-time wise. However it really should give you a warning to point out the code is nonsensical, which is what I'll re-purpose this bug as a request to add.

Totally makes sense! Sorry for the confusion (I'm very new to Verilog) :)

#3 Updated by Wilson Snyder 11 months ago

  • Status changed from Feature to NoFixNeeded

Wasn't a bug, forgot to close earlier.

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