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Author Name: Kevin Townsend Original Redmine Issue: 1297 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
For example having the port: "input signed a" will lead to the following error:
syntax error, unexpected IDENTIFIER, expecting '['
I don't know what the official Verilog spec is, but VCS does allow this. If this isn't allow, the error could be clearer.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-04-01T11:52:43Z
This was reported by another user last week, and is already fixed in the git version (but not released yet).
Thanks for the report though!
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Author Name: Kevin Townsend
Original Redmine Issue: 1297 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
For example having the port: "input signed a" will lead to the following error:
syntax error, unexpected IDENTIFIER, expecting '['
I don't know what the official Verilog spec is, but VCS does allow this. If this isn't allow, the error could be clearer.
The text was updated successfully, but these errors were encountered: