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Issue #1297

1 Bit signed values

Added by Kevin Townsend over 1 year ago. Updated over 1 year ago.

Status:
Duplicate
Priority:
Low
Assignee:
Category:
TranslationError
% Done:

0%

Estimated time:
8.00 h

Description

For example having the port: "input signed a" will lead to the following error:

syntax error, unexpected IDENTIFIER, expecting '['

I don't know what the official Verilog spec is, but VCS does allow this. If this isn't allow, the error could be clearer.

History

#1 Updated by Wilson Snyder over 1 year ago

  • Category set to TranslationError
  • Status changed from New to Duplicate
  • Assignee set to Wilson Snyder

This was reported by another user last week, and is already fixed in the git version (but not released yet).

Thanks for the report though!

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