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Issue #1298

Port direction on structs parsed as "interface"!

Added by Amal Khailtash almost 2 years ago. Updated almost 2 years ago.

Status:
NoFixNeeded
Priority:
Normal
Assignee:
-
% Done:

0%


Description

Some port directions defined as struct are parsed as "interface". I have a simple script that I use for instantiating a block. Here is the example output:

$ perl vinst.pl s_mod.sv

%Error: s_mod.sv:29: syntax error, unexpected IDENTIFIER, expecting ')' or ',' s_mod s_mod__i ( .sz ( sz ), // interface s_t2 - .clk ( clk ), // in logic - .sx ( sx ), // interface s_t1 - .q ( q ), // out logic - .s_t1 ( s_t1 ), // in - .d ( d ) // in logic [7:0] - );

Files are attached. Regards, -- Amal

s_mod.tar.bz2 (1.62 KB) Amal Khailtash, 04/10/2018 06:52 PM

s_mod.tar.bz2 (1.63 KB) Amal Khailtash, 04/11/2018 12:53 PM

History

#1 Updated by Amal Khailtash almost 2 years ago

Some port directions defined as struct are parsed as "interface". I have a simple script that I use for instantiating a block. Here is the example output:

$ perl vinst.pl s_mod.sv

%Error: s_mod.sv:29: syntax error, unexpected IDENTIFIER, expecting ')' or ','
  s_mod s_mod__i (
    .sz   ( sz   ),  // interface s_t2        - 
    .clk  ( clk  ),  // in     logic       - 
    .sx   ( sx   ),  // interface s_t1        - 
    .q    ( q    ),  // out    logic       - 
    .s_t1 ( s_t1 ),  // in                 - 
    .d    ( d    )   // in     logic [7:0] - 
  );

Files are attached.

Regards,
-- Amal

#2 Updated by Wilson Snyder almost 2 years ago

  • Status changed from New to NoFixNeeded

Your file isn't valid SystemVerilog, you are only importing the s_t type (which happens not to exist). You need to import all types used, e.g. s_t1 and s_t2 or just "s_pkg::*".

#3 Updated by Amal Khailtash almost 2 years ago

Sorry, I hastily modified the files before packing them. The problem is more like if the type definition is in an include file, I see this problem.

I fixed the testcase and is attached.

s_t1 is defined in "s_inc.svh" and that seems to be not seen. Typedef s_t2 that is not in an include is seen and direction/type is correct.

%Error: s_mod.sv:31: syntax error, unexpected IDENTIFIER, expecting ')' or ','
%Error: s_mod.sv:33: syntax error, unexpected ')', expecting ',' or ';'
  s_mod s_mod__i (
    .sz   ( sz   ),  // out    s_t2        - 
    .clk  ( clk  ),  // in     logic       - 
    *.sx   ( sx   ),  // interface s_t1        -* 
    .q    ( q    ),  // out    logic       - 
    *.s_t1 ( s_t1 ),  // in                 -* 
    .d    ( d    )   // in     logic [7:0] - 
  );

It would be nice to have a distinction between wire type (wire/reg) and datatype on ports/signals.

Regards,

#4 Updated by Wilson Snyder almost 2 years ago

You forgot to pass options=>$opt to your Verilog::Netlist - see the example in the Verilog::Netlist manpage.

As to wires vs regs, the Netlist::Net net_type accessor should give you that information.

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