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Port direction on structs parsed as "interface"! #1298
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Original Redmine Comment Some port directions defined as struct are parsed as "interface". I have a simple script that I use for instantiating a block. Here is the example output:
Files are attached. |
Original Redmine Comment Your file isn't valid SystemVerilog, you are only importing the s_t type (which happens not to exist). You need to import all types used, e.g. s_t1 and s_t2 or just "s_pkg::*". |
Original Redmine Comment Sorry, I hastily modified the files before packing them. The problem is more like if the type definition is in an include file, I see this problem. I fixed the testcase and is attached. s_t1 is defined in "s_inc.svh" and that seems to be not seen. Typedef s_t2 that is not in an include is seen and direction/type is correct.
It would be nice to have a distinction between wire type (wire/reg) and datatype on ports/signals. Regards, |
Original Redmine Comment You forgot to pass options=>$opt to your Verilog::Netlist - see the example in the Verilog::Netlist manpage. As to wires vs regs, the Netlist::Net net_type accessor should give you that information. |
Author Name: Amal Khailtash
Original Redmine Issue: 1298 from https://www.veripool.org
Some port directions defined as struct are parsed as "interface". I have a simple script that I use for instantiating a block. Here is the example output:
$ perl vinst.pl s_mod.sv
%Error: s_mod.sv:29: syntax error, unexpected IDENTIFIER, expecting ')' or ','
s_mod s_mod__i (
.sz ( sz ), // interface s_t2 -
.clk ( clk ), // in logic -
.sx ( sx ), // interface s_t1 -
.q ( q ), // out logic -
.s_t1 ( s_t1 ), // in -
.d ( d ) // in logic [7:0] -
);
Files are attached.
Regards,
-- Amal
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