Author Name: Filipe Rosset
Original Redmine Issue: 1299 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Fedora bug report: https://bugzilla.redhat.com/show_bug.cgi?id=1551668

perl: v5.26.2
gcc: gcc-8.0.1
glibc-2.27

No tests defined for Verilog::Preproc extension.
make[1]: Leaving directory '/home/filiperosset/rpmbuild/my/iverilog-deps/perl-Verilog-Perl/Verilog-Perl-3.448/Preproc'
PERL_DL_NONLAZY=1 "/usr/bin/perl" "-MExtUtils::Command::MM" "-MTest::Harness" "-e" "undef Test::Harness::Switches; test_harness(0, 'blib/lib', 'blib/arch')" t/.t
t/00_pod.t ........... ok
t/01_manifest.t ...... ok
t/02_help.t .......... ok
t/03_spaces.t ........ ok
t/04_critic.t ........ ok
t/05_yaml.t .......... ok
t/10_keywords.t ...... ok
t/12_splitbus.t ...... ok
t/14_numbers.t ....... ok
t/16_std.t ........... ok
t/20_getopt.t ........ ok
t/30_preproc.t ....... ok
t/32_noinc.t ......... ok
t/33_gzip.t .......... ok
t/34_parser.t ........ ok
t/35_sigparser.t .....
Failed 3/6 subtests
t/36_sigmany.t ....... ok
t/40_netlist.t ....... ok
t/41_example.t ....... ok
t/42_dumpcheck.t ..... ok
t/43_storable.t ...... ok
t/44_create.t ........ ok
t/46_link.t .......... ok
t/48_leak.t .......... ok
t/49_largeish.t ...... ok
t/50_vrename.t ....... ok
t/51_vrename_kwd.t ... ok
t/56_editfiles.t ..... ok
t/58_vsplitmodule.t .. ok
t/60_vpassert.t ...... ok
t/80_vppreproc.t ..... ok
t/85_vhier.t ......... ok
Failed 1/33 test programs. 0/471 subtests failed.
t/86_vhier_tick.t .... ok

Test Summary Report

t/35_sigparser.t (Wstat: 134 Tests: 3 Failed: 0)
Non-zero wait status: 134
Parse errors: Bad plan. You planned 6 tests but ran 3.
Files=33, Tests=471, 7 wallclock secs ( 0.14 usr 0.06 sys + 4.83 cusr 0.80 csys = 5.83 CPU)
Result: FAIL
make: *** [Makefile:968: test_dynamic] Error 255
erro: Status de saída de /var/tmp/rpm-tmp.YVeiPA inválido (%check)
Status de saída de /var/tmp/rpm-tmp.YVeiPA inválido (%check)