You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Author Name: John Dickol
Original Redmine Issue: 13 from https://www.veripool.org
Original Date: 2008-06-04
Original Assignee: Wilson Snyder (@wsnyder)
This may be an enhancment vs. a bug.
I'm using vhier to find all the files used in my design + testbench. It doesn't like the SV interfaces I'm using. Specifically, the following items within an interface cause errors:
port list
signal (wire, etc.) definitions
clocking blocks
always blocks
Here's a sample file to illustrate the problem. The error messages I get are embedded as comments in the file. I used ifdefs to exclude the unsupported code and proceed to the next error.
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-06-04T16:55:46Z
The Verilog::Parser (what vhier uses) doesn't yet understand SystemVerilog interfaces.
This will be done at some point, but not soon. If you'd like to help out getting this working, let me know.
Author Name: John Dickol
Original Redmine Issue: 13 from https://www.veripool.org
Original Date: 2008-06-04
Original Assignee: Wilson Snyder (@wsnyder)
This may be an enhancment vs. a bug.
I'm using vhier to find all the files used in my design + testbench. It doesn't like the SV interfaces I'm using. Specifically, the following items within an interface cause errors:
Here's a sample file to illustrate the problem. The error messages I get are embedded as comments in the file. I used ifdefs to exclude the unsupported code and proceed to the next error.
vhier_ifc.sv:
The text was updated successfully, but these errors were encountered: