$version Generated by VerilatedVcd $end
$date Sun May  6 20:36:08 2018
 $end
$timescale   1ps $end

 $scope module top $end
  $scope module top $end
    $var wire  1 # clk $end
    $var wire  1 $ fastclk $end
    $var wire 40 - in_quad [39:0] $end
    $var wire  2 , in_small [1:0] $end
    $var wire 70 / in_wide [69:0] $end
    $var wire 40 ' out_quad [39:0] $end
    $var wire  2 & out_small [1:0] $end
    $var wire 70 ) out_wide [69:0] $end
    $var wire  1 % reset_l $end
    $scope module sub $end
     $var wire  1 # clk $end
     $var wire 32 2 count_c [31:0] $end
     $var wire 32 3 count_f [31:0] $end
     $var wire  1 $ fastclk $end
     $var wire  1 % reset_l $end
    $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end