Id: 	25833
Status: 	resolved
Worked: 	5 min
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	WSNYDER <wsnyder@>
Requestors: 	NODINE <nodine@>

Severity: 	Important
Broken in:

     * 2.341
     * 2.372

X Attachments
addsr.v

     * Mon Mar 26 18:20:46 2007 (1.2k) by NODINE

Subject: 	Fails to parse first statement after null port list

The Verilog::SigParser never calls the signal_decl routine for the
declaration of reg "a". The problem is that $self->{is_signal_ok} is
false at the time the semicolon after the register declaration is
processed. This can be traced back to the line that says

1. Fallthru, more ; prep for next command is below

which does not, in fact, fall through to the rest of the ';' processing.
Subject: 	addsr.v

[application/tkgate 1.2k]
Message body not shown because it is too large or is not plain text.

I agree that's probably a problem, but the only place is_signal_ok is
set to 0 looks to be dead code.

When I run your verilog code using a hacked version of t/35_sigparser.t
I see all of the signals. Can you send me an example script that is broken?

BTW I'm sorry the parser isn't bison'ized yet.

Subject: 	Re: [rt.cpan.org #25833] Fails to parse first statement after null port list
Date: 	Thu, 29 Mar 2007 15:43:02 -0500
To: 	bug-Verilog-Perl@
From: 	Mark Nodine <nodine@>

When I worked on a simple example, it was fine. When I
ran my full program using perl 5.8.8 instead of 5.8.0, it
was fine. The full script failed on 5.8.0.

So I guess you shouldn't worry about it.

Sorry to trouble you.

--Mark

I've released 2.373 which fixes this bug.