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Issue #1313

AUTOINST problem for module containing clocking block

Added by David Rogoff over 1 year ago. Updated 6 months ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
Autos
% Done:

0%


Description

I just created a simple clock/reset module to instantiate in my testbench. The module contains a clocking block:

   default clocking tb_cb @(posedge clk);
     default input #1step output #2ps;
     output      rst;
   endclocking // tb_cb

When I instantiated the module and expanded it, it added

   i_clk_rst_gen
     (/*AUTOINST*/
      // Outputs
      .clk                            (clk),
      .rst                            (rst),
      .2ps                            (2ps),
      // Inputs
      .1step                            (1step));

Looks like the input and output keywords in the default line are confusing AUTOINST.

Easy fix?

Thanks,

David

History

#1 Updated by Wilson Snyder over 1 year ago

  • Status changed from New to AskedReporter

There is some code in place to skip over the clocking. Can you attach a self-contained test? Thanks.

#2 Updated by David Rogoff over 1 year ago

Before expansion:

module clk_rst_gen
  (output logic clk, rst);

   default clocking tb_cb @(posedge clk);
   default input #1step output #2ps;
   output      rst;
endclocking // tb_cb

   initial begin : clk_gen
      clk  = 0;
      forever
        #5  clk = ~clk;
   end : clk_gen

   initial begin : rst_gen
      rst  = 1;
      repeat (5) @tb_cb;
      rst <= 0;
   end : rst_gen
endmodule : clk_rst_gen

module tb;
   /*AUTOLOGIC*/

   clk_rst_gen  i_clk_rst_gen
     (/*AUTOINST*/);
endmodule : tb

After expansion:

module tb;
   /*AUTOLOGIC*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   logic        clk;            // From i_clk_rst_gen of clk_rst_gen.v
   logic        rst;            // From i_clk_rst_gen of clk_rst_gen.v
   // End of automatics

   clk_rst_gen  i_clk_rst_gen
     (/*AUTOINST*/
      // Outputs
      .clk                            (clk),
      .rst                            (rst),
      .2ps                            (2ps),
      // Inputs
      .1step                            (1step));
endmodule : tb

Also, note that the indentation is messed up for the clocking block.

David

#3 Updated by Wilson Snyder over 1 year ago

  • Status changed from AskedReporter to Confirmed

I made a stab at this but it needs more time as broke clocking modports.

Basically the parser needs to change to understand "default clocking foo;" does not start a declaration, but "default clocking foo @(...);" does.

#4 Updated by David Rogoff 6 months ago

Hi Wilson.

I just hit this problem again and wondered if there's been any activity on it during the past year.

Thanks,

David

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