Id: 	26141
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	NODINE <nodine@>

Severity: 	Important
Broken in:

     * 2.372
     * 2.373

Fixed in: 	3.000
X Attachments
wireassign.v

     * Fri Apr 06 16:27:55 2007 (58b) by NODINE

Subject: 	Combined wire declaration/assignments

A wire declaration that combines an assignment results in incorrect
information being passed to signal_decl.

In the attached file, signal_decl gets called correctly with "b@"
and then incorrectly with "a[2]" and "b[2]" (a re-declaration).

Using perl5.8.0 and perl 5.8.8 on Linux.
Subject: 	wireassign.v

[application/tkgate 58b]
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