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indentation of coverpoint is incorrect if coverpoint expression is a concatenation #1321

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veripoolbot opened this issue Jun 20, 2018 · 4 comments
Closed

indentation of coverpoint is incorrect if coverpoint expression is a concatenation #1321

veripoolbot opened this issue Jun 20, 2018 · 4 comments
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Author Name: Robert Swan
Original Redmine Issue: 1321 from https://www.veripool.org

Coverpoints on curly-brace concatenations indent incorrectly, and accumulate indent level.

module m;
    bit a, b, c;
    covergroup g;
       cp_ab: coverpoint {a,b} {
                                bins one = {1};
                                bins two = {2};
                                }
         cp_bc: coverpoint {b,c} {
                                  bins one = {1};
                                  bins two = {2};
                                  }
           endgroup
endmodule

Desired/correct indenting is seen if an iff clause is added to the coverpoints:

module m;
    bit a, b, c;
    covergroup g;
       cp_ab: coverpoint {a,b} iff (1) {
          bins one = {1};
          bins two = {2};
       }
       cp_bc: coverpoint {b,c} iff (1) {
          bins one = {1};
          bins two = {2};
       }
    endgroup
endmodule

Verilog-mode version is 2018-05-26-be4eda3-vpo.
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-06-20T14:57:39Z

Yes, looks wrong. The indentation code is presently without a major maintainer, so it might be a while before this is fixed unless you can provide a patch.

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Original Redmine Comment
Author Name: Robert Swan
Original Date: 2018-07-06T01:39:18Z

The following is working for me:

verilog-mode version 2018-05-26-be4eda3-vpo:

module m;
    bit[0:0] a, b, c;
    covergroup g;
       cp_ab: coverpoint {a,b} {
                                bins one = {1};
                                bins two = {2};
                                }

         cp_ab_if_c: coverpoint {a,b} iff c {
            bins one = {1};
            bins two = {2};
         }

         cp_ab_if_c_slice: coverpoint {a,b} iff c[0] {
                                                      bins one = {1};
                                                      bins two = {2};
                                                      }

           cp_a_if_bc: coverpoint {a,b} iff {b,c} {
                                                   bins one = {1};
                                                   bins two = {2};
                                                   }

             cp_a_slice : coverpoint a[0] {
                                           bins one = {1};
                                           bins two = {2};
                                           }

               cp_a_slice_if_b : coverpoint a[0] iff b {
                  bins one = {1};
                  bins two = {2};
               }

               cp_a_if_b_slice : coverpoint a iff b[0] {
                                                        bins one = {1};
                                                        bins two = {2};
                                                        }

                 cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] {
                                                                   bins one = {1};
                                                                   bins two = {2};
                                                                   }
                   endgroup
endmodule

Patch:

diff --git a/verilog-mode.el-2018-05-26-be4eda3-vpo b/verilog-mode.el-indent-fix
index f7f757f..a5a3617 100644
--- a/verilog-mode.el-2018-05-26-be4eda3-vpo
+++ b/verilog-mode.el-indent-fix
@@ -6450,6 +6450,34 @@ Return >0 for nested struct."
                                                 "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
                                                 "\\|with\\)\\>\\|" verilog-in-constraint-re)))
                             (setq pass 1)))))
+
+          ;; step backwards over coverpoint/iff on concatenation/slice
+          (catch 'coverpoint-or-iff
+            (dotimes (test-coverpoint-or-iff 4)
+              (if (looking-at "coverpoint")
+                  (progn
+                    (verilog-beg-of-statement)
+                    (setq pass 1)
+                    (throw 'coverpoint-or-iff nil)))
+              (if (equal (char-after) ?\})
+                  (progn
+                    (forward-char 1)
+                    (backward-list)
+                    (verilog-backward-sexp))
+                (if (equal (char-after) ?\[)
+                    (progn 
+                      (verilog-backward-token)
+                      (verilog-backward-sexp)
+                      )
+                  (if (or (looking-at "iff"))
+                      (progn
+                        (verilog-backward-ws&directives)
+                        (verilog-backward-token))
+                    (if (eq pass 0)
+                        (progn
+                          (verilog-backward-ws&directives)
+                          (verilog-backward-sexp))))))))
+
            (if (eq pass 0)
                (progn (goto-char pt) nil) 1)))
      ;; not

Patched:

module m;
    bit[0:0] a, b, c;
    covergroup g;
       cp_ab: coverpoint {a,b} {
          bins one = {1};
          bins two = {2};
       }

       cp_ab_if_c: coverpoint {a,b} iff c {
          bins one = {1};
          bins two = {2};
       }

       cp_ab_if_c_slice: coverpoint {a,b} iff c[0] {
          bins one = {1};
          bins two = {2};
       }

       cp_a_if_bc: coverpoint {a,b} iff {b,c} {
          bins one = {1};
          bins two = {2};
       }

       cp_a_slice : coverpoint a[0] {
          bins one = {1};
          bins two = {2};
       }

       cp_a_slice_if_b : coverpoint a[0] iff b {
          bins one = {1};
          bins two = {2};
       }

       cp_a_if_b_slice : coverpoint a iff b[0] {
          bins one = {1};
          bins two = {2};
       }

       cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] {
          bins one = {1};
          bins two = {2};
       }
    endgroup
endmodule

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-07-12T12:13:43Z

Great work this passes on your new test, but if you could please download the git tree and try the self tests this fails with an error "wrong type argument: consp"

Also a nit, in Lisp rather than this

   (if (a)
       (foo)
     (if (b)
          (bar)
       (if (c)
           (baz))))

do this

   (cond
    ((a)
     (foo))
    ((b)
     (bar))
    ((c)
     (baz)))

If not clear I'll clean it up for you.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-21T15:16:17Z

Still awaiting a patch+test.

gmlarumbe added a commit to gmlarumbe/verilog-mode that referenced this issue May 10, 2022
@gmlarumbe
Fix issue veripool#1321: incorrect indentation of coverpoints
c88609d 
Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
@gmlarumbe gmlarumbe mentioned this issue May 11, 2022
Merged
wsnyder pushed a commit that referenced this issue May 12, 2022
@gmlarumbe
Fix indentation of coverpoints (#1321) (#1766).
95df088 
* verilog-mode.el (verilog-at-constraint-p): Fix indentation of coverpoints (#1321) (#1766).

Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
@wsnyder wsnyder closed this as completed May 12, 2022
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