Author Name: John DeRoo
Original Redmine Issue: 1324 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

I have inherited a System Verilog test environment that has a top.sv that instantiates the dut and which also has an initial block to run the phases of the testing. It uses a macro passed in from the command line to define the file that has the specific test that is to be run. So, at the top of the file, it has

`include `TEST

However, emacs mode complains "Can't find Verilog-read-defines file: 'TEST", which I more or less expected. So I created a trivial test file and added

`ifndef TEST
`define TEST "./empty_test.sv"
`endif

before the include. I still get the same error. As a test, I commented out the include `TEST and replaced it with

`include "./empty_test.sv"

And that worked. I then changed the `include back and ran emacs -q to make sure there was nothing in my .emacs that overrode defaults - still had the problem. To see if there was something else in the design that was causing the problem I took the files involved and stripped them down to what I think is the bare minimum, and the problem remained. At the end of the file I have a fairly standard emacs-mode footer:

///////////////////////////////////////////////////////////////////////////////
// Local Variables:
// verilog-library-directories: (".")
// eval:(verilog-read-defines)
// eval:(verilog-read-includes)
// End:

I don't really like the model of using command line arguments to define the file to be included, but that seems to be pretty widespread in this environment and I need to resolve several other bigger issues before I change that aspect of the environment. Am I doing something wrong? Is there some way to get verilog mode to either expand the TEST before evaluating the include, or just ignore this construction altogether?

If it helps, I can provide the test files.

Thanks,
John DeRoo