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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-07-18T22:26:40Z
Verilog-mode does not in the general case handle any `defines, it's too difficult, sorry.
It seems like there's a standard name for your `defines, you could maintain a local copy of verilog-mode where you look for this define and skip over the contents; obviously this wouldn't be something that would work in general but might be ok for your purposes.
Another possible local hack is you could have emacs expand the define when it reads in, and write it back in the strange form, somewhat similar to how .* expands and saves.
Author Name: Joe Orth
Original Redmine Issue: 1325 from https://www.veripool.org
I have a module definition like:
module moduleA
(
input `pkg_rev_sym(pkgB,typeB) vara
);
NOTE: the text macro that is required because of our group's coding standards.
When I autoinst this, I get the following:
Showing up in the port list. I also get something similar that shows up when I do a .* expansion.
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