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Issue #1326

Comb Logic order problem

Added by Kyunghwan Cho 8 months ago. Updated 7 months ago.

Status:
AskedReporter
Priority:
Normal
Assignee:
-
Category:
-
% Done:

0%


Description

When trying to compile systemverilog source, I found the following issues.

alu0_opd_update reflects the previous value of alu0_c, not the current value of alu0_c. At verilated cpp file, I checked that the line of alu0_opd_update is before that of alu0_c.

logic alu0_c;
logic alu0_opd_update;

assign   alu0_c = (i_exe_alu0_c == 2'b00) |
              (i_exe_alu0_c == 2'b01 && status_true) | (i_exe_alu0_c == 2'b10 && ~status_true);
assign   alu0_opd_update = i_exe_alu0_update_enable & alu0_c & update_alu;

Using always_comb to enforce order of assignments, it works fine.

always_comb begin alu0_c = (i_exe_alu0_c 2'b00) | (i_exe_alu0_c 2'b01 && status_true) | (i_exe_alu0_c == 2'b10 && ~status_true); alu0_opd_update = i_exe_alu0_update_enable & alu0_c & update_alu;

History

#1 Updated by Kyunghwan Cho 8 months ago

always_comb begin 
alu0_c = (i_exe_alu0_c 2'b00) | (i_exe_alu0_c 2'b01 && status_true) | (i_exe_alu0_c == 2'b10 && ~status_true); 
alu0_opd_update = i_exe_alu0_update_enable & alu0_c & update_alu;
end

#2 Updated by Wilson Snyder 7 months ago

  • Status changed from New to AskedReporter

Verilator internally should treat assigns identically to always_comb, so probably something more complicated is going on.

Can you please make a standalone test ideally in test_regress format?

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