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Support LXT2 file format natively #1333
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Original Redmine Comment I used this repo rather than the patch: https://github.com/johnjohnlin/verilator_fork/tree/lxt2 Great work! Here's the feedback on your patches. If any of these are hard/non-obvious I can clean them up for you.
Probably better to this automatically when --trace-lxt2 is specified with
then add a new "sub lxt2vcd" to driver.pl? This can then give an appropriate error if it isn't installed (similar "sub vcd_identical").
Once that is done the t_trace_lxt2.v might not have anything special it in and can be removed. I suspect once you do this you'll see you need the other full/chg functions ;)
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Original Redmine Comment Thanks for reviewing this patch. I just pushed a new version and fixed most of the problems except for these two:
It seems that it is not necessary, the Makefile installs @include/.[vch]@.
Sorry I don't know how to do that because I did not write Perl before.
Yes, it should be added in the future. |
Original Redmine Comment Please pull from the #�_lxt2 branch of the http://git.veripool.org/git/verilator repository as I made some cleanups and additions to your version. Then please fix the following tests
Also separately, for the changes you made to the lxt2 sources (changing the include to "", and the casts) can you please file a bug with Bybell to get these upstreamed to gtkWave. Getting close, thanks! |
Original Redmine Comment Hello, the new version is updated to "this branch":https://github.com/johnjohnlin/verilator_fork/tree/#�_lxt2 . |
Original Redmine Comment Excellent, made a few more minor cleanups and pushed to git towards 4.000. Thanks for your good work. |
Original Redmine Comment Hello, the linker fails if I trace a vector with more than 32 bits. I have an undefined reference to "VerilatedLxt2::quad2Str(unsigned long, int)"
I am using GCC 7.3.0 under Cygwin 64-bit. I have double-checked the generated code, nothing seems to be wrong. Verilog code :
Vecp5_jtag_spi_top.h : VL_SIG64(ecp5_jtag_spi_top__DOT__r_er1_dr,47,0); Vecp5_jtag_spi_top__Trace__Slow.cpp : vcdp->fullQuad (c+41,(vlTOPp->ecp5_jtag_spi_top__DOT__r_er1_dr),48); Vecp5_jtag_spi_top__Trace.cpp : vcdp->chgQuad (c+41,(vlTOPp->ecp5_jtag_spi_top__DOT__r_er1_dr),48); Any clue ? Regards, Frederic |
Original Redmine Comment Quad-word dumping is tested correctly in @t_trace_complex_lxt2@ (acf4a3).
It should give something like
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Original Redmine Comment Hello,
The first line is from "Vecp5_jtag_spi_top__ALLsup.o", the second one from "verilated_lxt2_c.o". Those do match the linker error. Why vluint64_t does not generate the same type in both files, I do not know. Regards, Frederic |
Original Redmine Comment By putting warning pragmas in verilatedos.h, I can see that Vecp5_jtag_spi_top__ALLsup.cpp got compiled with "typedef unsigned long vluint64_t;" (good behaviour) and other .cpp files with "typedef unsigned long long vluint64_t;" (wrong behaviour). If I revert back to VCD tracing, I see the same typedef issue but the linker does not complain. Very strange. Frederic |
Original Redmine Comment Solved by including <sys/types.h> in verilatedos.h. It looks like an old bug that never got caught. Frederic |
Original Redmine Comment Thanks for debugging! I added a sys/types include, this seems to set __WORDSIZE. It has to be conditional on the OS, so please see if the current git works for you. |
Original Redmine Comment Yep, it works. Thank you. |
Original Redmine Comment In 4.002, thanks for your work. |
Original Redmine Comment Note based on your LXT2 code/changes we just committed adding FST format to git, please give it a try, if there are issues please file a new bug. Our hope is to eventually have fancier SystemVerilog type support in FST. |
Author Name: Yu Sheng Lin (@johnjohnlin)
Original Redmine Issue: 1333 from https://www.veripool.org
Original Assignee: Yu Sheng Lin (@johnjohnlin)
I make a issue about "this development thread":https://www.veripool.org/boards/3/topics/2601-Verilator-A-way-to-support-LXT2-file-format-natively .
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