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Issue #1338

--trace of SystemVerlog string gives compile error

Added by Iztok Jeras 8 months ago. Updated 7 months ago.

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Using Verilator Verilator 3.924 2018-06-12 (an Ubuntu build hosted as launchpad PPA), and the latest systemC from the same PPA. So it is possible the tools are not compiled properly.

The SystemVerilog code compiles without errors, but the generated C++ does not compile:
In file included from Vrp_tb__ALLsup.cpp:3:0:
Vrp_tb__Trace.cpp: In static member function ‘static void Vrp_tb::traceChgThis__2(Vrp_tb__Syms*, VerilatedVcd*, uint32_t)’:
Vrp_tb__Trace.cpp:65:62: error: no matching function for call to ‘VerilatedVcd::chgQuad(int, std::__cxx11::string&, int)’
  vcdp->chgQuad (c+1,(vlSymsp->TOP__riscv_asm_pkg.REG_X[0]),64);
Steps to reproduce the error:
git clone
cd rp32/
git checkout Verilator_string_bug
cd sim/
make -f Makefile.verilator 

bugreport.tgz - tarball containing test (195 KB) Iztok Jeras, 09/05/2018 07:53 PM

bugreport.tgz (196 KB) Iztok Jeras, 09/12/2018 05:24 PM


#1 Updated by Iztok Jeras 8 months ago

The offending code (if I comment it out it compiles properly) is a function returning a SV string:

The error is present regardless if the function is actually used or not, but I tried using it, just in case it would help (it did not):

#2 Updated by Wilson Snyder 8 months ago

  • Status changed from New to AskedReporter

Your rp32.git seemed to pass on my current master, can you try using the latest code, and if it doesn't pass make a minimal test ideally in test_regress format - sounds like you reduced it quite a bit. Thanks

#3 Updated by Iztok Jeras 8 months ago

I was able to strip the test down to the basics, but I have not yet created a test_regress unit. I should be able to, I have done this before :)

I was able to reproduce the issue with the git HEAD version of Verilator.

While striping I first removed the SystemC dependency, ... the last part to be removed was the sprintf() function.

It seems the parameter/localparameter of type array of strings is causing the issue.

#4 Updated by Iztok Jeras 8 months ago

Hi, I updated the string regression test and run "make test", and there was no error, but I am unsure if the test was actually executed. I added a $display debug line into the test bus not able to see it in the make test output, so I am assuming I did something wrong.

The updated test is available here:

#5 Updated by Iztok Jeras 8 months ago

I will attach a tarball containing my build with all generated files, so you would be able to see if there are errors in the generated code. If there are no errors inside generated code, then a make inside odj_dir should not fail. Now the sources are minimized to 3 short files (Makefile, .cpp, .sv) all in a single directory.

tar -xvf bugreport.tgz cd bugreport/sim export VERILATOR_ROOT=??? make

#6 Updated by Wilson Snyder 8 months ago

  • Status changed from AskedReporter to Resolved
  • Assignee set to Wilson Snyder

Fixed in git towards 4.000. Note the fix is not to trace the string at all, as VCD format isn't speced to have string support.

#7 Updated by Iztok Jeras 7 months ago

I was able to run the test code properly with the fixed Verilator, then I encountered another error compiling generated code.

I tried to make the test case smaller (it is now about 20 lines), but if I remove additional lines of code the code compiles and runs properly. Verilator Git HEAD from a couple of days ago was used.

I again attached a tarball containing the example and generated code. The rebuild process is the same as with the previous tarball.

Regards, Iztok Jeras

#8 Updated by Wilson Snyder 7 months ago

Please file a new issue and I'll take a look tonight, thanks.

#9 Updated by Iztok Jeras 7 months ago

#10 Updated by Wilson Snyder 7 months ago

  • Subject changed from error related to use of SystemVerlog string type to --trace of SystemVerlog string gives compile error

#11 Updated by Wilson Snyder 7 months ago

  • Status changed from Resolved to Closed

In 4.002.

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