New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
AUTOINST enhancement (range expressions) #1346
Comments
Original Redmine Comment Attaching patch that worked for me. |
Original Redmine Comment Note that verilog code with syntax errors like "output [w2<>w1:0] y2;" would reduce to "[:0]". The suggested patch (line 10581) may be changed to so that above verilog code reduces to "[4<>2:0] y2". Either is fine. |
Original Redmine Comment Good work. Can you please create an updated patch?
Thanks! |
Original Redmine Comment
|
Original Redmine Comment Pushed to git and verilog-mode-2018-09-18-74c0fda-vpo.el I made one change, to fix your earlier issue I think you moved the <> replacement outside the loop, this isn't good as it won't properly replace multiple shifts. I instead make sure there's no leading <>'s. The results passed your tests, but please give it a try. |
Original Redmine Comment Thanks. Your release worked fine for me. Yes, I moved <> replacement outside the loop but then also added another pass of "(while (not (equal last-pass out)", thinking multiple shifts would be replaced correctly (at least as seen in the test I wrote). I'll try to fail my patch and update the test case. |
Author Name: Maghawan Punde
Original Redmine Issue: 1346 from https://www.veripool.org
Original Assignee: Maghawan Punde
I want to request an enhancement to Verilog mode AUTOINST.
Here is snippet of ports in module being instantiated.
Here is how it expands for me.
Will it be possible to evaluate expressions with "/", "<<", ">>", "<<<" or ">>>"?
The text was updated successfully, but these errors were encountered: