Author Name: Gary Hammes
Original Redmine Message: 2741 from https://www.veripool.org

I haven't been able to configure the indent of the io after a module declaration's open parenthesis. I'm putting the
open parenthesis on it's own line to make the io list indent consistent. Verilog mode wants to indent the io list an
additional space. Everything else is configured to follow the style of indents being 4 characters in my case. I
want the io list to aligned to the parenthesis, or 0 indent. Is there a configuation for this setting that I am overlooking?

Thanks
-Gary

///////////////////
// Actual indent output
///////////////////
module example_indent
     (
      input wire         clk,
      input wire         reset_n,

///////////////////
// Desired indent output
///////////////////
module example_indent
     (
     input wire         clk,
     input wire         reset_n,