Adding support for passing by reference
Verilator currently doesn't support passing variables by reference and results in:
[UNKNOWN]: Unsupported: SystemVerilog 2005 reserved word not implemented: ref
This would be quite useful to have if it allows us to avoid creating temporary variables and copying them across when attempting to store results from tasks/functions in structures.
#1 Updated by Wilson Snyder about 2 months ago
- Status changed from New to Resolved
- Assignee set to Wilson Snyder
Fixed in git towards 4.008.
I added only a few simple tests, I expect some problems as you try to use refs. Please file a new bug on any problems and try to update the new test_regress/t/t_var_ref.pl test to show the problem(s). Thanks!
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