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Issue #1360

Adding support for passing by reference

Added by Jake Longo 2 months ago. Updated 16 days ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Unsupported
% Done:

0%


Description

Verilator currently doesn't support passing variables by reference and results in:

[UNKNOWN]: Unsupported: SystemVerilog 2005 reserved word not implemented: ref

This would be quite useful to have if it allows us to avoid creating temporary variables and copying them across when attempting to store results from tasks/functions in structures.

History

#1 Updated by Wilson Snyder about 2 months ago

  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Fixed in git towards 4.008.

I added only a few simple tests, I expect some problems as you try to use refs. Please file a new bug on any problems and try to update the new test_regress/t/t_var_ref.pl test to show the problem(s). Thanks!

#2 Updated by Wilson Snyder 16 days ago

  • Status changed from Resolved to Closed

In 4.008.

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