Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

False BLKANDNBLK error for different signals in a vector #1365

Closed
veripoolbot opened this issue Nov 6, 2018 · 1 comment
Closed

False BLKANDNBLK error for different signals in a vector #1365

veripoolbot opened this issue Nov 6, 2018 · 1 comment
Labels
resolution: duplicate Closed; issue or pull request already exists

Comments

@veripoolbot
Copy link
Contributor


Author Name: Al Grant
Original Redmine Issue: 1365 from https://www.veripool.org


module conflict(input clk, input b, output wire [1:0] a);
  reg [1:0] r;
  always @(posedge clk)
     r[0] <= b;
  always @*
     r[1] = 1'b0;
  assign a = r;
endmodule

fails with

%Error-BLKANDNBLK: conflict.v:2: Unsupported: Blocked and non-blocking assignments to same variable: conflict.r

This is surely legal as they are distinct signals.

Also, it would be helpful if the erorr message could reference the line of the two assignments (and, if in a generate loop, the value of genvars), instead of just the declaration.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-11-07T18:42:49Z


Please see #�.

I understand this is annoying, but is a fairly high effort limitation to resolve so hasn't been worked on.

@veripoolbot veripoolbot added the resolution: duplicate Closed; issue or pull request already exists label Dec 22, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
resolution: duplicate Closed; issue or pull request already exists
Projects
None yet
Development

No branches or pull requests

1 participant