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Issue #1369

Raise error / warning on continous assignment to reg

Added by Peter Gerst 9 months ago. Updated 8 days ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Lint
% Done:

0%


Description

Verilator does not throw error / warning on continuous assignment to a register. See the following example:

content of wire_test.v:
module wire_test (
    input clk,
    input rst,
    input in1,
    input in2,
    input mux,
    output reg out
);

// caught by verilator git version 15af70
// wire internal_reg;
reg internal_reg;
reg out_muxed;

always @(posedge clk) begin
    if (rst) begin
        internal_reg <= 1'b0;
    end else begin
        internal_reg <= in1;
    end
end

assign out_muxed = (mux) ? internal_reg: in2;
assign out = (rst) ? out_muxed : 1'b0;

endmodule

Calling verilator as verilator --lint-only wire_test.v does not complain about the assignment on internal_reg and out registers.

git version of verilator is used (last commit on Nov 26) but the issue is also present in version 4.006:
$ git log -n 1
commit 15af706286212c933595ba8228d2d334fb81e0f7 (HEAD -> master, origin/master, origin/HEAD)
Author: Wilson Snyder <wsnyder@wsnyder.org>
Date:   Mon Nov 26 19:09:08 2018 -0500

    Fix crash due to cygwin bug in getline, bug1349.

This issue is in connection with forum message https://www.veripool.org/boards/3/topics/1559-Verilator-Verilator-fails-to-warn-error-on-procedural-assignment-to-wire that seems to be corrected: Procedural assignment to wire causes error message to be thrown using git version referenced above.

History

#1 Updated by Wilson Snyder 9 months ago

  • Status changed from New to Feature

I believe the code sent is legal in SystemVerilog, so no warning is appropriate. What complains and does it support SystemVerilog?

#2 Updated by Peter Gerst 9 months ago

Xilinx ISE 14.7 syntheser complains about this:
ERROR:HDLCompiler:329 - "wire_test\wire_test.v" Line 23: Target <out_muxed> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "wire_test\wire_test.v" Line 24: Target <out> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:598 - "wire_test\wire_test.v" Line 1: Module <wire_test> ignored due to previous errors.

I need to use this syntheser for Spartan 6 targets. As far as I know it does not support SystemVerilog. (https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/sim.pdf page 11 and 101)

I also forgot to mention that I use verilator with specifying the Verilog standard that ISE supports. For linting verilator is called in the following way:

verilator --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY wire_test.v

#3 Updated by Wilson Snyder 9 months ago

  • Subject changed from verilator does not raise error / warning on continous assignment to reg to Raise error / warning on continous assignment to reg
  • Status changed from Feature to Resolved
  • Assignee set to Wilson Snyder

Fixed in git towards 4.008.

#4 Updated by Wilson Snyder 9 months ago

  • Status changed from Resolved to Closed

In 4.008.

#5 Updated by Peter Gerst 9 months ago

Thank you for the fix! verilator now raises error on internal_reg but does not recognize the case of out signal in the example code above.

#6 Updated by Kris Jeon 8 days ago

In order to raise the warning for port, I've changed like the following:

In 'V3ParseGrammar.cpp'

AstVar* V3ParseGrammar::createVariable(FileLine* fileline, string name,
                                       AstNodeRange* arrayp, AstNode* attrsp) {
    AstNodeDType* dtypep = GRAMMARP->m_varDTypep;
    UINFO(5,"  creVar "<<name<<"  decl="<<GRAMMARP->m_varDecl
          <<"  io="<<GRAMMARP->m_varIO<<"  dt="<<(dtypep?"set":"")<<endl);
    // added lines -->
    if (v3Global.opt.lintOnly() && !fileline->language().systemVerilog()
        && GRAMMARP->m_varDecl == AstVarType::PORT && GRAMMARP->m_varIO == VDirection::OUTPUT && (!dtypep)) {
        GRAMMARP->m_varDecl = AstVarType::WIRE;
    } // <--
...

In 'V3ParseGrammar.cpp'

    virtual void visit(AstNodeVarRef* nodep) {
        // Any variable
        if (nodep->lvalue()
            && !VN_IS(nodep, VarXRef)) {  // Ignore interface variables and similar ugly items
            if (m_inProcAssign && !nodep->varp()->varType().isProcAssignable()) {
                nodep->v3warn(PROCASSWIRE, "Procedural assignment to wire, perhaps intended var" 
                              " (IEEE 2017 6.5): " 
                              +nodep->prettyName());
            }
            if (m_inContAssign && !nodep->varp()->varType().isContAssignable()
                && !nodep->fileline()->language().systemVerilog()) {
                nodep->v3warn(CONTASSREG, "Continuous assignment to reg, perhaps intended wire" 
                              " (IEEE 2005 6.1; Verilog only, legal in SV): " 
                              +nodep->prettyName());
            }
            // added lines -->
            if (v3Global.opt.lintOnly() && m_inContAssign && nodep->varp()->varType() == AstVarType::PORT
                && !nodep->fileline()->language().systemVerilog()) {
                nodep->v3warn(CONTASSREG, "Continuous assignment to reg, perhaps intended wire" 
                              " (IEEE 2005 6.1; Verilog only, legal in SV): " 
                              +nodep->prettyName());
            } // <--
        }

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