Raise error / warning on continous assignment to reg
Verilator does not throw error / warning on continuous assignment to a register. See the following example:content of wire_test.v:
module wire_test ( input clk, input rst, input in1, input in2, input mux, output reg out ); // caught by verilator git version 15af70 // wire internal_reg; reg internal_reg; reg out_muxed; always @(posedge clk) begin if (rst) begin internal_reg <= 1'b0; end else begin internal_reg <= in1; end end assign out_muxed = (mux) ? internal_reg: in2; assign out = (rst) ? out_muxed : 1'b0; endmodule
Calling verilator as
verilator --lint-only wire_test.v does not complain about the assignment on internal_reg and out registers.
$ git log -n 1 commit 15af706286212c933595ba8228d2d334fb81e0f7 (HEAD -> master, origin/master, origin/HEAD) Author: Wilson Snyder <firstname.lastname@example.org> Date: Mon Nov 26 19:09:08 2018 -0500 Fix crash due to cygwin bug in getline, bug1349.
This issue is in connection with forum message https://www.veripool.org/boards/3/topics/1559-Verilator-Verilator-fails-to-warn-error-on-procedural-assignment-to-wire that seems to be corrected: Procedural assignment to wire causes error message to be thrown using git version referenced above.
#2 Updated by Peter Gerst 7 months ago
ERROR:HDLCompiler:329 - "wire_test\wire_test.v" Line 23: Target <out_muxed> of concurrent assignment or output port connection should be a net type. ERROR:HDLCompiler:329 - "wire_test\wire_test.v" Line 24: Target <out> of concurrent assignment or output port connection should be a net type. ERROR:HDLCompiler:598 - "wire_test\wire_test.v" Line 1: Module <wire_test> ignored due to previous errors.
I need to use this syntheser for Spartan 6 targets. As far as I know it does not support SystemVerilog. (https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/sim.pdf page 11 and 101)
I also forgot to mention that I use verilator with specifying the Verilog standard that ISE supports. For linting verilator is called in the following way:
verilator --lint-only --default-language 1364-2001 -Wall -Wno-PINCONNECTEMPTY wire_test.v
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