Support top-level tristate ports #1373
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
effort: days
Expect this issue to require roughly days of invested effort to resolve
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Stephen Richardson
Original Redmine Issue: 1373 from https://www.veripool.org
DESCRIPTION of the bug:
Top level has bidirectional port bus1 and direction bit en1. When
en1==0, bus1 is used as an input port, else it is an output port.
When bus1 is an output it reads an internal id code (13333).
A result port emits the value (bus1+10000).
Then test harness sets en1==1 for five clock cycles, hoping to see
result 23333, which succeeds.
Then test harness sets en1==0 and writes sequential values (1,2,3,4,5) to
bus1, hoping to see result (10001,10002,10003,10004,10005).
This fails, we see only zeroes on bus1 (below).
Why?
MANIFESTATION of the bug:
Need: top.v, harness.cpp (see below)
Do: ./build_and_run.sh
...which does something like this:
NOTES on the bug:
This combo (below), in Vtop.cpp, overwrites values trying to come in on port
"inout bus1" via the harness.
harness.cpp
top.v
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