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SystemVerilog array initialization crashes verilator with no useful error message #1378

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veripoolbot opened this issue Dec 18, 2018 · 2 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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@veripoolbot
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Author Name: Viktor Tomov
Original Redmine Issue: 1378 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


If we have a SV packed structure with several elements and we try to initialize it as an array list, but the array list is inconsistent (see the code below), the verilator crashes with no useful message.


`include "test_module_pkg.svh"


module test_module
(
     input logic                         sys_clk,
     input logic                         sys_rst_n,
     input logic                         sys_ena,

     input test_module_pkg::test_type_t  test_in,
     output test_module_pkg::test_type_t test_out
);


import test_module_pkg::*;

  
always_ff @(posedge sys_clk or negedge sys_rst_n) begin
     if (~sys_rst_n) begin
         test_out <= '{'0, '0, '0};
     end
     else begin
         if(sys_ena) begin
             test_out.t1 <= ~test_in.t1;
             test_out.t2 <= ~test_in.t2;
             test_out.t3 <= ~test_in.t3;
         end
         else begin
             test_out <= '{'0, '0}; /* Inconsistent array list; */
         end
     end
end

endmodule: test_module

</code>
`ifndef TEST_MODULE_PKG
`define TEST_MODULE_PKG

package test_module_pkg;
     
     typedef struct packed
     {
         logic t1;
         logic t2;
         logic t3;
     } test_type_t;

endpackage : test_module_pkg

`endif /* TEST_MODULE_PKG */ 

</code>
viktor@ubuntu:~/projects/tests/struct_not_full_init$ verilator -cc test_module_pkg.svh test_module.sv --debug
	/usr/local/bin/verilator_bin_dbg -cc test_module_pkg.svh test_module.sv --debug
Starting Verilator 4.009 devel rev UNKNOWN_REV
- V3Os.cpp:57:        export SYSTEMC_ARCH=linux # From sysname 'linux'
- V3File.cpp:264:        --check-times failed: out-of-date test_module.sv; 739=?743 1545139969.694888261=?1545139466.636026919 1545139969.694888261=?1545139466.636026919
- V3GraphTest.cpp:358:selfTest: 
- V3ParseImp.cpp:114: parseFile: test_module_pkg
  Preprocessing test_module_pkg.svh
- V3PreShell.cpp:136:     Reading test_module_pkg.svh
- V3ParseImp.cpp:171: Lexing test_module_pkg.svh
- V3ParseImp.cpp:114: parseFile: test_module
  Preprocessing test_module.sv
- V3PreShell.cpp:136:     Reading test_module.sv
- V3PreShell.cpp:136:     Reading test_module_pkg.svh
- V3ParseImp.cpp:171: Lexing test_module.sv
- V3LinkCells.cpp:190:Link Module: PACKAGE 0x560e936c64e0 <e3#> {d4} u4=0x560e936c65f0  test_module_pkg  L0 [LIB]
- V3LinkCells.cpp:190:Link Module: MODULE 0x560e936c9870 <e24#> {e5} u4=0x560e936c9980  test_module  L0
dot -Tpdf -o ~/a.pdf obj_dir/Vtest_module_pkg_001_linkcells.dot
- V3LinkLevel.cpp:50: modSortByLevel()
- V3Ast.cpp:1045:     Dumping obj_dir/Vtest_module_pkg_002_cells.tree
- V3LinkDot.h:40:     linkDotPrimary: 
- V3LinkJump.cpp:259: linkJump: 
- V3Ast.cpp:1045:     Dumping obj_dir/Vtest_module_pkg_007_link.tree
- V3Param.cpp:792:    param: 
- V3LinkDot.h:45:     linkDotParamed: 
- V3Ast.cpp:1045:     Dumping obj_dir/Vtest_module_pkg_009_paramlink.tree
- V3Dead.cpp:423:     deadifyModules: 
- V3Width.cpp:3962:   width: 
%Error: export VERILATOR_ROOT=
%Error: /usr/local/bin/verilator_bin_dbg -cc test_module_pkg.svh test_module.sv --debug
%Error: Command Failed /usr/local/bin/verilator_bin_dbg -cc test_module_pkg.svh test_module.sv --debug
</code>
@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2018-12-19T01:42:57Z


Thanks for the good report.

Simple fix, fixed in git towards 4.010.

@veripoolbot
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-01-28T12:32:20Z


In 4.010.

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Labels
area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed
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