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task T;
output s;
assign s = 1'b0;
endtask
module #�(output a[2:0]);
integer i = 1;
initial begin
T(a[i]);
end
endmodule
fails with
%Error: Internal Error: bugs/#�.sv:10: ../V3AstNodes.cpp:764: Can't find current statement to addBeforeStmt
Strangely, this is sensitive to the vector size, and (for me) it stops happening if the '2' is changed to '3'. That might suggest sensitivity to uninitialized data but valgrind isn't showing anything.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-01-05T10:51:55Z
The problem is internal code isn't treating the task reference as a statement; working on a fix as touches a lot of code.
You may workaround this issue by adding some statement around the task reference, e.g. "if (i>=0 || i<=2) T(a[i]);"
This error doesn't occur when you use 3:0 because it's now a power of two so there's no test needed to suppress the array assignment if i=3.
This code is race-free in Verilator, but caution that this code is nondeterministic and may race in simulators that predate SystemVerilog 2012, as "integer i=0" is not guaranteed to happen before the initial block uses it.
Author Name: Al Grant
Original Redmine Issue: 1387 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
fails with
Strangely, this is sensitive to the vector size, and (for me) it stops happening if the '2' is changed to '3'. That might suggest sensitivity to uninitialized data but valgrind isn't showing anything.
The text was updated successfully, but these errors were encountered: