Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Internal error when task is used to assign subscripted vector #1387

Closed
veripoolbot opened this issue Jan 4, 2019 · 3 comments
Closed

Internal error when task is used to assign subscripted vector #1387

veripoolbot opened this issue Jan 4, 2019 · 3 comments
Assignees
Labels
resolution: fixed Closed; fixed

Comments

@veripoolbot
Copy link
Contributor


Author Name: Al Grant
Original Redmine Issue: 1387 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


task T;
  output s;
  assign s = 1'b0;
endtask

module #�(output a[2:0]);
  integer i = 1;
  initial begin
     T(a[i]);
  end
endmodule

fails with

%Error: Internal Error: bugs/#�.sv:10: ../V3AstNodes.cpp:764: Can't find current statement to addBeforeStmt

Strangely, this is sensitive to the vector size, and (for me) it stops happening if the '2' is changed to '3'. That might suggest sensitivity to uninitialized data but valgrind isn't showing anything.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-01-05T10:51:55Z


The problem is internal code isn't treating the task reference as a statement; working on a fix as touches a lot of code.

You may workaround this issue by adding some statement around the task reference, e.g. "if (i>=0 || i<=2) T(a[i]);"

This error doesn't occur when you use 3:0 because it's now a power of two so there's no test needed to suppress the array assignment if i=3.

This code is race-free in Verilator, but caution that this code is nondeterministic and may race in simulators that predate SystemVerilog 2012, as "integer i=0" is not guaranteed to happen before the initial block uses it.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-01-06T22:38:54Z


Fixed in git towards 4.010.

@veripoolbot
Copy link
Contributor Author


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-01-28T12:32:34Z


In 4.010.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
resolution: fixed Closed; fixed
Projects
None yet
Development

No branches or pull requests

2 participants