Author Name: Berk Akinci
Original Redmine Issue: 1390 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

I want to report a bug.
Before I go further, I want to say that Verilog mode has changed my life... :-)
I've taken a look at the Verilog-Mode FAQ.

To reproduce the bug, start a fresh Emacs via emacs and open the attached file named "autoregtest.v"
When I C-c, C-a with this file, AUTOREG generates automatic "reg" lines for some wires that I expect to pass through from module to output port.
If I let "AUTOINST" create these module outputs, all is OK. (In my real-world use, I need to override the wire name for multiple instances.)
If I explicitly declare the ANSI style output as wire, all is OK. (e.g "output wire [1:0] out")

I didn't expect the "reg" lines to be generated. This had me chasing my tail for a while trying to figure out what I was missing. I don't think there is anything syntactically incorrect, but AUTOREG insists on declaring registers.

The key parts from the attached file are:
module autoregtest
(...
output [BITS-1:0] out
);

/*AUTOWIRE*/

/*AUTOREG*/

autoregtest_module #(...)
instance_a (.out			(out),
       /*AUTOINST*/);

endmodule

Emacs : GNU Emacs 26.1 (build 1, x86_64-unknown-cygwin)
of 2018-05-28
Package: verilog-mode v2019-01-02-47b88f2-vpo

current state:

(setq
verilog-active-low-regexp nil
verilog-after-save-font-hook nil
verilog-align-ifelse nil
verilog-assignment-delay ""
verilog-auto-arg-sort nil
verilog-auto-declare-nettype nil
verilog-auto-delete-trailing-whitespace nil
verilog-auto-endcomments t
verilog-auto-hook nil
verilog-auto-ignore-concat nil
verilog-auto-indent-on-newline t
verilog-auto-inout-ignore-regexp nil
verilog-auto-input-ignore-regexp nil
verilog-auto-inst-column 40
verilog-auto-inst-dot-name nil
verilog-auto-inst-interfaced-ports nil
verilog-auto-inst-param-value nil
verilog-auto-inst-sort nil
verilog-auto-inst-template-numbers nil
verilog-auto-inst-vector t
verilog-auto-lineup 'declarations
verilog-auto-newline t
verilog-auto-output-ignore-regexp nil
verilog-auto-read-includes nil
verilog-auto-reset-blocking-in-non t
verilog-auto-reset-widths t
verilog-auto-save-policy nil
verilog-auto-sense-defines-constant nil
verilog-auto-sense-include-inputs nil
verilog-auto-star-expand t
verilog-auto-star-save nil
verilog-auto-template-warn-unused nil
verilog-auto-tieoff-declaration "wire"
verilog-auto-tieoff-ignore-regexp nil
verilog-auto-unused-ignore-regexp nil
verilog-auto-wire-type nil
verilog-before-auto-hook nil
verilog-before-delete-auto-hook nil
verilog-before-getopt-flags-hook nil
verilog-before-save-font-hook nil
verilog-cache-enabled t
verilog-case-fold t
verilog-case-indent 2
verilog-cexp-indent 2
verilog-compiler "echo 'No verilog-compiler set, see "M-x describe-variable verilog-compiler"'"
verilog-coverage "echo 'No verilog-coverage set, see "M-x describe-variable verilog-coverage"'"
verilog-delete-auto-hook nil
verilog-getopt-flags-hook nil
verilog-highlight-grouping-keywords nil
verilog-highlight-includes t
verilog-highlight-modules nil
verilog-highlight-translate-off nil
verilog-indent-begin-after-if t
verilog-indent-declaration-macros nil
verilog-indent-level 3
verilog-indent-level-behavioral 3
verilog-indent-level-declaration 3
verilog-indent-level-directive 1
verilog-indent-level-module 3
verilog-indent-lists t
verilog-library-directories '(".")
verilog-library-extensions '(".v" ".sv")
verilog-library-files nil
verilog-library-flags '("")
verilog-linter "echo 'No verilog-linter set, see "M-x describe-variable verilog-linter"'"
verilog-minimum-comment-distance 10
verilog-mode-hook 'verilog-set-compile-command
verilog-mode-release-emacs nil
verilog-mode-version "2019-01-02-47b88f2-vpo"
verilog-preprocessor "vppreproc FLAGS FILE"
verilog-simulator "echo 'No verilog-simulator set, see "M-x describe-variable verilog-simulator"'"
verilog-tab-always-indent t
verilog-tab-to-comment nil
verilog-typedef-regexp nil
verilog-warn-fatal nil
)