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Issue #1400

Bug: verilator sometimes fails to detect electrical short

Added by Will Korteland 7 months ago. Updated 6 months ago.

Status:
Closed
Priority:
Normal
Assignee:
Category:
Lint
% Done:

0%


Description

Hi,

When building the attached code (should be able to simply type "make"), verilator doesn't detect the electrical short, and will also generate invalid C++. The specific error I get is:

In file included from Vmod__ALLcls.cpp:3:
Vmod.cpp: In static member function ‘static void Vmod::_settle__TOP__1(Vmod__Syms*)’:
Vmod.cpp:98:55: error: lvalue required as left operand of assignment
     (QData)((IData)(vlTOPp->mod__DOT__sig)) = vlTOPp->mod__DOT____Vcellout__submodule_inst__out;
My GCC version is:
g++ (GCC) 8.2.1 20181215 (Red Hat 8.2.1-6)
My verilator version is the one that came with Fedora:
Verilator 3.922 2018-03-17 rev verilator_3_920-32-gdf3d1a4

But I've also tested with verilator-git as of yesterday, and it still failed to detect the short.

A few points: the attached code is as minimal as I can get it. That said, if I narrow the output of `submodule` to 32b, verilator still won't detect the short but the code will be valid C++. If I avoid the concatenation entirely (see mod.sv), it detects the short and warns me.

Also, I had to leave `--trace` on for this to work, I assume to stop the relevant signal getting optimised away.

If you need any more info please let me know.

Thanks, - Will

repro.tar.gz (490 Bytes) Will Korteland, 02/19/2019 02:48 AM

History

#1 Updated by Wilson Snyder 7 months ago

  • Status changed from New to Resolved
  • Assignee set to Wilson Snyder

Fixed in git towards 4.012.

#2 Updated by Will Korteland 7 months ago

Wilson Snyder wrote:

Fixed in git towards 4.012.

Thanks!

#3 Updated by Wilson Snyder 6 months ago

  • Status changed from Resolved to Closed

In 4.012.

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