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When building the attached code (should be able to simply type "make"), verilator doesn't detect the electrical short, and will also generate invalid C++. The specific error I get is:
In file included from Vmod__ALLcls.cpp:3:
Vmod.cpp: In static member function ‘static void Vmod::_settle__TOP__1(Vmod__Syms*)’:
Vmod.cpp:98:55: error: lvalue required as left operand of assignment
(QData)((IData)(vlTOPp->mod__DOT__sig)) = vlTOPp->mod__DOT____Vcellout__submodule_inst__out;
My GCC version is:
g++ (GCC) 8.2.1 20181215 (Red Hat 8.2.1-6)
My verilator version is the one that came with Fedora:
But I've also tested with verilator-git as of yesterday, and it still failed to detect the short.
A few points: the attached code is as minimal as I can get it. That said, if I narrow the output of submodule to 32b, verilator still won't detect the short but the code will be valid C++. If I avoid the concatenation entirely (see mod.sv), it detects the short and warns me.
Also, I had to leave --trace on for this to work, I assume to stop the relevant signal getting optimised away.
If you need any more info please let me know.
Thanks,
Will
The text was updated successfully, but these errors were encountered:
Author Name: Will Korteland
Original Redmine Issue: 1400 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Hi,
When building the attached code (should be able to simply type "make"), verilator doesn't detect the electrical short, and will also generate invalid C++. The specific error I get is:
My GCC version is:
My verilator version is the one that came with Fedora:
But I've also tested with verilator-git as of yesterday, and it still failed to detect the short.
A few points: the attached code is as minimal as I can get it. That said, if I narrow the output of
submodule
to 32b, verilator still won't detect the short but the code will be valid C++. If I avoid the concatenation entirely (see mod.sv), it detects the short and warns me.Also, I had to leave
--trace
on for this to work, I assume to stop the relevant signal getting optimised away.If you need any more info please let me know.
Thanks,
The text was updated successfully, but these errors were encountered: