Original Redmine Comment
Author Name: David Rogoff
Original Date: 2019-02-26T18:36:18Z

Subject should be "does not work".

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-02-26T22:24:09Z

In Verilog, it's illegal to have an "assign" targeting a "reg", so I presume you're using system Verilog? Could you use "wire foo = bar" instead of assign?

If not I assume you're asking for an e.g. verilog-auto-reg-input-ignore-assign you set to "t"?

Original Redmine Comment
Author Name: David Rogoff
Original Date: 2019-02-27T18:08:08Z

Wilson Snyder wrote:

In Verilog, it's illegal to have an "assign" targeting a "reg", so I presume you're using system Verilog?

Correct

Could you use "wire foo = bar" instead of assign?

No, because the signals are output ports of the wrapper module, not internal signals

If not I assume you're asking for an e.g. verilog-auto-reg-input-ignore-assign you set to "t"?

I think so.

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-08T02:21:10Z

Added new verilog-auto-reg-input-assigned-ignore-regexp to verilog-mode-2019-03-07-4cfa499-vpo.

You'd use it like this at the bottom of your file for your case:

// Local Variables:
// verilog-auto-reg-input-assigned-ignore-regexp: ".*"
// End: