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I am trying to auto-connect using wires. According to the wiki
verilog-auto-wire (function)
Expand AUTOWIRE statements, as part of M-x verilog-auto. Make wire statements for instantiations outputs that aren't already declared. verilog-auto-wire-type may be used to change the datatype of the declarations.
When I run autos I expect to see a wire type created but instead I get "logic" type
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic outA; // From instA of dly.v, ...
// End of automatics
Here is my test module before expansion with autos:
Original Redmine Comment
Author Name: Mark Thompson
Original Date: 2019-02-22T00:50:28Z
Hello Wilson, thanks for pointing this out. The testcase is a simplified version of my RTL and did not behave the way my RTL did.
If anyone in the future facing a similar issue finds this bug, I finally figured out what is going on in my RTL. Turns out that if the instantiated module declares the port to be of type "logic" this bubbles up and replaces the verilog-auto-wire-type. Here is an updated example showing this. If you remove the "logic" keyword from the line
output logic outSig
then verilog-auto-wire-type works. If the "logic" keyword is present then it controls the declaration in the top module no matter what verilog-auto-wire-type is set to.
Author Name: Mark Thompson
Original Redmine Message: 2883 from https://www.veripool.org
I am trying to auto-connect using wires. According to the wiki
When I run autos I expect to see a wire type created but instead I get "logic" type
Here is my test module before expansion with autos:
The text was updated successfully, but these errors were encountered: