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Issue #1404

alignment within generate-if

Added by Warren Ferguson 5 months ago. Updated 5 months ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
-
% Done:

0%


Description

I entered the following file and allowed verilog mode (latest verilog-mode.el) to choose its own alignment. Why is the first generate-if using always_comb choosing the unusual alignment of the else block, whereas the generate-if using assigns has the expected alignment?

module test
  #(paramweter integer OPT = 1
    )
   (input logic y,z;
   );

   if (OPT = 1) begin
      always_comb begin
         y = 1'b1;
      end
end else begin
   always_comb begin
      y = 1'b0;
   end
end

   if (OPT = 1) begin
      assign z = 1'b1;
   end else begin
      assign z = 1'b0;
   end

endmodule // test

test.sv (349 Bytes) Warren Ferguson, 02/27/2019 09:38 PM

History

#1 Updated by Warren Ferguson 5 months ago

Attached source file given that code in text was not interpreted correctly.

#2 Updated by Wilson Snyder 5 months ago

  • Description updated (diff)
  • Status changed from New to Confirmed

Verilog-mode seems to mis-assume always_comb is left-most inside a module.

There might be a wait, generally indentation fixes will need to wait for someone to provide a patch.

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