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I entered the following file and allowed verilog mode (latest verilog-mode.el) to choose its own alignment. Why is the first generate-if using always_comb choosing the unusual alignment of the else block, whereas the generate-if using assigns has the expected alignment?
module test
#(paramweter integer OPT = 1
)
(input logic y,z;
);
if (OPT = 1) begin
always_comb begin
y = 1'b1;
end
end else begin
always_comb begin
y = 1'b0;
end
end
if (OPT = 1) begin
assign z = 1'b1;
end else begin
assign z = 1'b0;
end
endmodule // test
The text was updated successfully, but these errors were encountered:
Author Name: Warren Ferguson
Original Redmine Issue: 1404 from https://www.veripool.org
I entered the following file and allowed verilog mode (latest verilog-mode.el) to choose its own alignment. Why is the first generate-if using always_comb choosing the unusual alignment of the else block, whereas the generate-if using assigns has the expected alignment?
The text was updated successfully, but these errors were encountered: