Port defined as a net but used as a reg is not flagged as an error
I have a block with an output port that's supposed to be a declared as a reg, but I forgot to do so and Verilator didn't flag it as an error. However, both ModelSim and Icarus prevented the compilation from going through whereas Verilator compiled it just fine. Here's the test case:
module adder ( input rst_n, input clk, input [7:0] a, input [7:0] b, output [7:0] sum // should be "output reg [7:0] sum" ); always @ (posedge clk or negedge rst_n) if (!rst_n) begin sum <= 'h0; end else begin sum <= a + b; end endmodule
Icarus output is below:
$ iverilog adder.v adder.v:11: error: sum is not a valid l-value in adder. adder.v:6: : sum is declared here as wire. adder.v:14: error: sum is not a valid l-value in adder. adder.v:6: : sum is declared here as wire. 2 error(s) during elaboration.
ModelSim output is below:
-- Compiling module adder ** Error: adder.v(11): (vlog-2110) Illegal reference to net "sum". ** Error: adder.v(14): (vlog-2110) Illegal reference to net "sum".
Shouldn't Verilator compilation also fail? I am running Verilator 4.010.
#2 Updated by Wilson Snyder 14 days ago
- Status changed from Feature to WillNotFix
Looked further at this. In System Verilog this assignment is legal (as it's an sized type); note you didn't ask modelsim for SystemVerilog. I'm reluctant to spend time on warnings that don't apply to the more common SystemVerilog usage.
#3 Updated by Lloyd Gomez 13 days ago
Unfortunately I inherited the design with the construct above and it's a pure Verilog implementation, not SystemVerilog. I was trying to overhaul the existing testbench using Verilator. Just out of curiousity, I saved the adder example above to design.sv and tried to compile it using VCS on EDA Playground. I also got a compile error:
[2019-03-11 04:27:38 EDT] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' design.sv testbench.sv && ./simv +vcs+lic+wait Warning-[LNX_OS_VERUN] Unsupported Linux version Linux version 'CentOS Linux release 7.1.1503 (Core) ' is not supported on 'x86_64' officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE to linux or suse32 to override. Please refer to release notes for information on supported platforms. Warning-[LINX_KRNL] Unsupported Linux kernel Linux kernel '3.13.0-71-generic' is not supported. Supported versions are 2.4* or 2.6*. Chronologic VCS (TM) Version J-2014.12-SP1-1 -- Mon Mar 11 08:27:39 2019 Copyright (c) 1991-2014 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file 'design.sv' Parsing design file 'testbench.sv' Top Level Modules: tb TimeScale is 1 ns / 10 ps Error-[IBLHS-NT] Illegal behavioral left hand side design.sv, 11 Net type cannot be used on the left side of this assignment. The offending expression is : sum Source info: sum <= 'b0; Error-[IBLHS-NT] Illegal behavioral left hand side design.sv, 14 Net type cannot be used on the left side of this assignment. The offending expression is : sum Source info: sum <= (a + b); 2 errors CPU time: .076 seconds to compile Exit code expected: 0, received: 1
I tried VCS because the ModelSim I was given is old (10.1) and I wasn't sure about its SystemVerilog support to test the legality of the erroneous assignment.
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