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I have an systemverilog function like this, after press Tab key, the 'ref example_t' line is wrong indentation.
example_t is a self-defined class. It's still not working even though I add verilog-typedef-regexp:"_t$"
class example_t;
endclass // example_t
class test;
typedef class example_t;
virtual function void cmp_core
(
input bit [8:0] max_len,
input bit force_steep_443,
input bit mv,
ref example_t algo_cfg,
ref bit [17:0] orig_img [],
ref bit [15:0] cmp_img [],
input bit recmp_en = 1'b0,
input bit [17:0] prev_re = 18'b0,
output bit [17:0] re_pixel_output_tmp
);
endfunction // cmp_core
endclass // test
// Local Variables:
// verilog-typedef-regexp:"_t$"
// End:
P.S. My emacs version is 26.1 and verilog-mode.el was just cloned from github yesterday.
Thanks
The text was updated successfully, but these errors were encountered:
Author Name: Feng Chen (@chenfengrugao)
Original Redmine Message: 2927 from https://www.veripool.org
Hi all,
I have an systemverilog function like this, after press Tab key, the 'ref example_t' line is wrong indentation.
example_t is a self-defined class. It's still not working even though I add verilog-typedef-regexp:"_t$"
P.S. My emacs version is 26.1 and verilog-mode.el was just cloned from github yesterday.
Thanks
The text was updated successfully, but these errors were encountered: