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facing a error for verilatedvcdsc #1407

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veripoolbot opened this issue Mar 6, 2019 · 8 comments
Closed

facing a error for verilatedvcdsc #1407

veripoolbot opened this issue Mar 6, 2019 · 8 comments
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area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: abandoned Closed; not enough information or otherwise never finished

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Author Name: divyakumar shah (@divyashah98)
Original Redmine Issue: 1407 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

i am putting forward an error which i am facing


../sc_main.cpp: In function ‘int sc_main(int, char**)’:
../sc_main.cpp:34:27: error: invalid new-expression of abstract class type ‘VerilatedVcdSc’
 VerilatedVcdSc* tfp = new VerilatedVcdSc;
                            ^~~~~~~~~~~~~~
In file included from ../sc_main.cpp:3:0:
/usr/share/verilator/include/verilated_vcd_sc.h:38:7: note:   because the following virtual functions are pure within ‘VerilatedVcdSc’:
 class VerilatedVcdSc
        ^~~~~~~~~~~~~~
In file included from /usr/local/systemc-2.3/include/sysc/communication/sc_signal.h:40:0,
                  from /usr/local/systemc-2.3/include/sysc/communication/sc_buffer.h:34,
                  from /usr/local/systemc-2.3/include/systemc:79,
                  from /usr/local/systemc-2.3/include/systemc.h:219,
                  from ../sc_main.cpp:1:
/usr/local/systemc-2.3/include/sysc/tracing/sc_trace.h:97:18: note: 	virtual void sc_core::sc_trace_file::trace(const sc_core::sc_event&, const string&)
      virtual void trace( const tp& object,                                     \
                   ^
/usr/local/systemc-2.3/include/sysc/tracing/sc_trace.h:106:5: note: in expansion of macro ‘DECL_TRACE_METHOD_A’
      DECL_TRACE_METHOD_A( sc_event )
      ^~~~~~~~~~~~~~~~~~~
/usr/local/systemc-2.3/include/sysc/tracing/sc_trace.h:97:18: note: 	virtual void sc_core::sc_trace_file::trace(const sc_core::sc_time&, const string&)
      virtual void trace( const tp& object,                                     \
                   ^
/usr/local/systemc-2.3/include/sysc/tracing/sc_trace.h:107:5: note: in expansion of macro ‘DECL_TRACE_METHOD_A’
      DECL_TRACE_METHOD_A( sc_time )
      ^~~~~~~~~~~~~~~~~~~
Vleft.mk:59: recipe for target 'sc_main.o' failed
make: *** [sc_main.o] Error 1
make: Leaving directory '/home/divya/divya/verilog/leftv/obj_dir'

         SystemC 2.3.3-Accellera --- Feb 26 2019 21:53:20
         Copyright (c) 1996-2018 by all Contributors,
         ALL RIGHTS RESERVED

Warning: (W506) illegal characters: top verilog substituted by top_verilog
In file: ../../../src/sysc/kernel/sc_object.cpp:247

 out=0
 out=0
 out=1
 out=2
 out=4
 out=9
 out=19
 out=39
 out=79
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-07T00:07:37Z

I suspect you are missing a #include <systemc.h> in your sc_main file (see examples/tracing_sc/sc_main.cpp). If that's the case I'll fix the verilator header not to assume that.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-07T00:10:32Z

BTW if that doesn't work, to prefetch the next question please tell me the SYSTEMC_VERSION (from systemc's sysc/kernel/sc_ver.h) you are using.

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Original Redmine Comment
Author Name: divyakumar shah (@divyashah98)
Original Date: 2019-03-07T16:56:05Z

i am not missing systemc.h in my sc_main file
here my code

#include <systemc.h>
#include <Vleft.h>
#include <verilated_vcd_sc.h>

#include

int sc_main(int argc, char * argv[])
{

Verilated::commandArgs(argc,argv);

Verilated::traceEverOn(true);

sc_time T(1,SC_NS);
sc_clock clk("clk",T*20);

sc_signal<bool> in;
sc_signal<bool> clr;
sc_core::sc_signal<uint32_t> out;

Vleft* top = new Vleft("top");

top->clk(clk);
top->in(in);
top->clr(clr);
top->out(out);

VerilatedVcdSc* tfp = new VerilatedVcdSc;
top->trace(tfp, 10);
tfp->open("obj_dir/simu.vcd");

clr=1;
sc_start(10*T);
cout<<endl<<" out = "<<out;

clr=0;
sc_start(10*T);
cout<<endl<<" out = "<<out;


in=1;
sc_start(20*T);
cout<<endl<<" out = "<<out;


in=0;
sc_start(20*T);
cout<<endl<<" out = "<<out;

in=0;
sc_start(20*T);
cout<<endl<<" out = "<<out;


in=1;
sc_start(20*T);
cout<<endl<<" out = "<<out;


in=1;
sc_start(20*T);
cout<<endl<<" out = "<<out;


in=1;
sc_start(20*T);
cout<<endl<<" out = "<<out;



in=1;
sc_start(20*T);
cout<<endl<<" out = "<<out;



in=0;
sc_start(20*T);
cout<<endl<<" out = "<<out;

 

tfp->close();





delete top;

delete tfp;

return 0;

}

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Original Redmine Comment
Author Name: divyakumar shah (@divyashah98)
Original Date: 2019-03-07T16:59:27Z

for systemc version

#define SYSTEMC_2_3_3

#define SYSTEMC_VERSION 20181013

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-07T23:20:55Z

I test ok with 20181013. Your file looks ok. Please attach a complete tarball example - the file you attached doesn't have the include file at the line number of the rror you sent, so something is different.

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Original Redmine Comment
Author Name: divyakumar shah (@divyashah98)
Original Date: 2019-03-08T17:19:32Z

i am attaching files for which i am compiling . that is verilog rtl file left.v , testbench sc_main.cpp , text file for the error i am facing .please look into it and me if I made any mistake . thank you

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-03-08T23:14:31Z

using

verilator  -sc --exe -Wall --trace left.v sc_main.cpp
make -C obj_dir -f Vleft.mk

With the current git head, SystemC 2.3.3 and GCC 7.3.0 it works fine for me. You'll need to debug what is different in your system.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-10T00:29:57Z

Didn't hear back & presume you got it working. If you have tips to post for others that hit similar issues please update the bug.

@veripoolbot veripoolbot added area: configure/compiling Issue involves configuring or compilating Verilator itself resolution: abandoned Closed; not enough information or otherwise never finished labels Dec 22, 2019
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