Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Issue #1408

Support concatenation select

Added by Alexander Junk 7 months ago. Updated 5 months ago.

Status:
WillNotFix
Priority:
Low
Assignee:
-
Category:
-
% Done:

0%


Description

When trying to verilate multimux_out_2.v with

verilator --pins-bv 2 -sc multimux_out_2.v 

I get the error

%Error: multimux_out_2.v:34: syntax error, unexpected '[', expecting ',' or ';'
%Error: Exiting due to 1 error(s)
The assignment that is not working is:
assign \m3.q = { \m2.q , \m1.q }[select[0] +: 1];

When I replace the concatenation with an intermediate signal, everything works.

Yosys Open SYnthesis Suite also crashes when trying to import the design. See issue: [[https://github.com/YosysHQ/yosys/issues/870]]

multimux_out_2.v (1.26 KB) Alexander Junk, 03/13/2019 06:35 PM

History

#1 Updated by Wilson Snyder 7 months ago

  • Subject changed from Verilator can not verilate verilog design with concatenation and index access in the same assignment. to Support concatenation select
  • Status changed from New to Feature
  • Priority changed from High to Low

Two of the big three simulators do not appear to support select of concatenation of expressions, until they do I'm reluctant to add this as there are some complications. Perhaps someone else can provide a patch?

I added an error message that this is unsupported behavior versus a syntax error.

#2 Updated by Alexander Junk 7 months ago

Wilson Snyder wrote:

Two of the big three simulators do not appear to support select of concatenation of expressions, until they do I'm reluctant to add this as there are some complications. Perhaps someone else can provide a patch?

I added an error message that this is unsupported behavior versus a syntax error.

Thank you. The design was exported to verilog from yosys, which apparently generated the unsupported statement. I did not know that indexing does not work on a concatenation directly which is why I opened an issue here as well. So it is definitely a problem with the generated verilog not the parser.

#3 Updated by Wilson Snyder 5 months ago

  • Status changed from Feature to WillNotFix

As earlier commented, not supported by big simulators, so not fixing for now; if the others support this will revisit.

Also available in: Atom