Incorrect Result of Cascading Module Using Generate Statement #1409
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
resolution: no fix needed
Closed; no fix required (not a bug)
Author Name: Xusine Lin
Original Redmine Issue: 1409 from https://www.veripool.org
Hi. I use Verilator to verify a ripple carry adder formed by a series of full adders generated by generate statement of systemverilog, but I get a wrong result.
Here is my code:
And this is the accumulator using generate statement to create the ripple carry adder:
I run my test bench where I set
opA_i
to 1 and output the portresult_o
every cycle in Vivado 2018.3 and I get the correct result, but in Verilator I get the output like this:The text was updated successfully, but these errors were encountered: