Having trouble assigning signals of interfaces to regs within for loop
I experienced errors when I tried to assign signals of an interfaces array to 2-d regs. Attached are example files which can generate the errors below:
%Error: interface_for_loop_tb.sv:32: Expecting expression to be constant, but variable isn't const: i %Error: interface_for_loop_tb.sv:32: Could not expand constant selection inside dotted reference: i %Error: interface_for_loop_tb.sv:33: Expecting expression to be constant, but variable isn't const: i %Error: interface_for_loop_tb.sv:33: Could not expand constant selection inside dotted reference: i
Appreciate your help.
Regards, Junyi Xie
#1 Updated by Wilson Snyder 11 days ago
- Status changed from New to WillNotFix
Verilator currently requires interface (or cell) references must be statically unrolled. This is currently a fairly fundamental assumption that is unlikely to be improved in the near term (so not leaving this bug open).
To work around it move your for loop to become a generate loop outside the always.
And thanks for your good bug report, that makes it a lot easier to help.
for (genvar i = 0; i < 2; i++) begin always_comb begin buffer_a[i] = in_intfs[i].a; buffer_b[i] = in_intfs[i].b; end end
Hi Wilson, We come across a Xilinx page that suggests having for loop inside always_comb helps to save runtime.
This might be interesting for your investigation.
We will for now use the style you recommended though.
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