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Having trouble assigning signals of interfaces to regs within for loop #1418
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Original Redmine Comment Verilator currently requires interface (or cell) references must be statically unrolled. This is currently a fairly fundamental assumption that is unlikely to be improved in the near term (so not leaving this bug open). To work around it move your for loop to become a generate loop outside the always. And thanks for your good bug report, that makes it a lot easier to help.
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Original Redmine Comment This is reasonable. |
Original Redmine Comment Hi Wilson, https://www.xilinx.com/support/answers/55302.html This might be interesting for your investigation. We will for now use the style you recommended though. Thanks! |
Hi, I guess I have a similar problem. I want to select the next action based on a array of interfaces.
NB_CLIENTS is a parameter in this design. Therefore, I would expect that this for-loop can be easily unrolled an the interface with the highest number is selected. Unfortunately, I get the error message:
The first message points with ^ to the i, while the second message points to the [ bracket. I don't see why unrolling does not work here? Regards, |
You didn't indicate what cfg_addr_stream is. Regardless this would probably work
Note, in the future please avoiding posting to old closed issues for new questions, otherwise your question will likely get lost. |
Dear, cfg_addr_stream is an interface for a FIFO stream containing the valid signal. The basic idea of placing the code block in one always_comb is to force the synthesis to build-up a solution, which generates the IDLE state if none of the .valid signals is high. Your code has actually two always blocks, which drive the same signal and the order is not really defined, if I understood it right. Getting the original code running would be nice, nevertheless there is a work-around by converting the .valid signals of the interface into a logic array and then it should work. |
Author Name: Junyi Xie
Original Redmine Issue: 1418 from https://www.veripool.org
Hi Wilson,
I experienced errors when I tried to assign signals of an interfaces array to 2-d regs.
Attached are example files which can generate the errors below:
%Error: interface_for_loop_tb.sv:32: Expecting expression to be constant, but variable isn't const: i
%Error: interface_for_loop_tb.sv:32: Could not expand constant selection inside dotted reference: i
%Error: interface_for_loop_tb.sv:33: Expecting expression to be constant, but variable isn't const: i
%Error: interface_for_loop_tb.sv:33: Could not expand constant selection inside dotted reference: i
Appreciate your help.
Regards,
Junyi Xie
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