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Issue #1422

VPI hierarchy naming

Added by Stefan Wallentowitz 4 months ago. Updated about 2 months ago.

Status:
NoFixNeeded
Priority:
Normal
Assignee:
Category:
-
% Done:

0%


Description

Hi,

I am currently looking into coupling cocotb and Verilator and stumbled over one major issue, that can be solved in a couple of ways. I am wondering what you think about it and suggest as most acceptable solution.

Everything that has public access currently becomes accessible by its scope. But the naming at runtime always involves the toplevel wrapper name (TOP by default), while cocotb operates on the full names in the actual verilog hierarchy. So, there are a couple of options:

1. Push it to cocotb and prepend the top name. This is not overly complex, but a bit cumbersome.

2. Change the hierarchy naming in Verilator entirely. This is a mess as it will break a lot of existing code.

3. Follow Verilog hierarchy naming in VPI. This seems to be the right place and has the least impact.

So, my proposal is to implement 3. I can do it as part of my effort and send as the first patch.

What do you think?

Cheers, Stefan

History

#1 Updated by Wilson Snyder 4 months ago

  • Status changed from New to Feature

I agree 3 makes the most sense. Perhaps the TOP should also be suppressed in %m messages, that is it will look to run time as if TOP doesn't exist for VPI and output messages.

#2 Updated by Wilson Snyder about 2 months ago

Stumbled into some other code related to handling TOP, note the existing code allows passing "" when constructing a model and the "TOP" prefix (from the user's model instantiation) will no longer appear in %m messages.

#3 Updated by Wilson Snyder about 2 months ago

  • Status changed from Feature to NoFixNeeded

See last msg, think this will make naming compatible, if not please reopen.

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