Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Issue #1425

Sensitivity lists with boolean expressions

Added by Al Grant 7 months ago. Updated 7 months ago.

Status:
WillNotFix
Priority:
Normal
Assignee:
-
Category:
-
% Done:

0%


Description

Items in sensitivity lists can be expressions:
always @(&vec) ..
This is legal, as long as you remember that "always (a|b)" isn't the same as "always (a or b)". This came up before in Bug #934 but was not resolved. It sounded like this would need deep changes to Verilator. But would it not be possible to do it by a simple transformation? I.e. any time you see
always @(expr1 or ...) ..
and an expression is not simple, just introduce an assign:
assign tmp1234 = expr1;
always @(tmp1234 ...)
This is exactly the transformation you would do at the source level if working around this Verilator limitation. So there would be no impact on Verilator's simulation engine. Unless I'm missing something?

History

#1 Updated by Wilson Snyder 7 months ago

  • Status changed from New to WillNotFix

Verilator doesn't really do anything with sensitivity lists except posedge/negedge handling; it basically is following synthesis rules, not event simulator rules. If you add the wire as you suggest it will act just as if it's in an "always @*", which is unlikely to be what you want.

Also available in: Atom