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Problem with list of memories #143

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veripoolbot opened this issue May 9, 2007 · 0 comments
Closed

Problem with list of memories #143

veripoolbot opened this issue May 9, 2007 · 0 comments
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Author Name: Mark Nodine
Original Redmine Issue: 143 from https://www.veripool.org
Original Date: 2007-05-09
Original Assignee: Wilson Snyder (@wsnyder)

This bug was cloned from Perl-RT, rt27036.

Email addresses have have been truncated.

Id: 	27036
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	NODINE <nodine@>

Severity: 	Normal
Broken in: 	2.373
Fixed in: 	3.000
X Attachments
lh_memcat.v

     * Wed May 09 14:28:11 2007 (1.7k) by NODINE

Wed May 09 14:28:11 2007 NODINE - Ticket created

Subject: 	Problem with list of memories

In the attached file, registers "a_fifo_cam_indices" and
"lt_fifo_cam_indices" do not have their memory bounds correctly
initialized when Verilog::SigParser calls the signal_decl callback.
Furthermore, the vector comes in as "@[3:0] [3:0]".
Subject: 	lh_memcat.v

[application/tkgate 1.7k]
Message body not shown because it is too large or is not plain text.

Wed Jun 13 12:32:56 2007 WSNYDER - Fixed in 3.000 added

Wed Jun 13 12:32:57 2007 WSNYDER - Status changed from 'new' to 'resolved'
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