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Scalar memory parsed as vector #144

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veripoolbot opened this issue May 9, 2007 · 0 comments
Closed

Scalar memory parsed as vector #144

veripoolbot opened this issue May 9, 2007 · 0 comments
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Author Name: Mark Nodine
Original Redmine Issue: 144 from https://www.veripool.org
Original Date: 2007-05-09
Original Assignee: Wilson Snyder (@wsnyder)


This bug was cloned from Perl-RT, rt27037.

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Id: 	27037
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	NODINE <nodine@>

Severity: 	Normal
Broken in: 	2.373
Fixed in: 	3.000
X Attachments
memidxrng.v

     * Wed May 09 14:52:47 2007 (1.6k) by NODINE

Wed May 09 14:52:47 2007 NODINE - Ticket created

Subject: 	Scalar memory parsed as vector

In the attached file, the scalar memory "mem" parses as
reg [12:2] mem;
instead of
reg mem [12:2];
in the callbacks of Verilog::SigParser to signal_decl.
Subject: 	memidxrng.v

[application/tkgate 1.6k]
Message body not shown because it is too large or is not plain text.

Wed Jun 13 12:32:43 2007 WSNYDER - Fixed in 3.000 added

Wed Jun 13 12:32:44 2007 WSNYDER - Status changed from 'new' to 'resolved'

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