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Issue #1446

SystemVerilog interface indentation in module declaration

Added by Clarke Watson 8 months ago. Updated 8 months ago.

Status:
Confirmed
Priority:
Normal
Assignee:
-
Category:
Indents
% Done:

0%


Description

Hi,

Thanks for creating and maintaining verilog-mode. It is awesome!

I am having trouble getting SystemVerilog interfaces inside module declarations to indent properly when using verilog-batch-indent.

See attached sample code.

I would expect the din and dout interfaces to be aligned with the same column as the discrete logic signals after running verilog-batch-indent, but there always seems to be just a single space between the port type (SV interface) and the port name.

Let me know if I am missing a setting in the verilog-mode.el file.

Thanks! Clarke

test.sv (480 Bytes) Clarke Watson, 05/23/2019 04:47 PM

History

#1 Updated by Wilson Snyder 8 months ago

  • Project changed from Verilog-Perl to Verilog-mode
  • Status changed from New to Confirmed
  • Assignee deleted (Wilson Snyder)

Agreed it should indent as you indicate, in general this looks to verilog-mode like a user-defined type, which is misindented due to bug386.

Unfortunately unless you can contribute a patch, the indent part of verilog-mode is looking for a maintainer so it might be a long wait.

#2 Updated by Wilson Snyder 8 months ago

  • Category set to Indents

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