Author Name: Clarke Watson
Original Redmine Issue: 1446 from https://www.veripool.org

Hi,

Thanks for creating and maintaining verilog-mode. It is awesome!

I am having trouble getting SystemVerilog interfaces inside module declarations to indent properly when using verilog-batch-indent.

See attached sample code.

I would expect the din and dout interfaces to be aligned with the same column as the discrete logic signals after running verilog-batch-indent, but there always seems to be just a single space between the port type (SV interface) and the port name.

Let me know if I am missing a setting in the verilog-mode.el file.

Thanks!
Clarke