Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

AUTOs fails with embedded ifndef in parameters #1448

Closed
veripoolbot opened this issue May 26, 2019 · 4 comments
Closed

AUTOs fails with embedded ifndef in parameters #1448

veripoolbot opened this issue May 26, 2019 · 4 comments
Assignees
@wsnyder
Labels
autos wontfix

Comments

@veripoolbot
Copy link
Collaborator

Author Name: Ray Stevens
Original Redmine Issue: 1448 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Hi Mac,

I was using this version of verilog-mode:
You are using verilog-mode 2019-05-06-28bee25-vpo

To reproduce the issue, recompute AUTOs on attached ip0301 file. You should see this error message:
Updating AUTOs...
or: ip0301_cpuSubsystem.sv:209: Can’t locate ‘`endif’ module definition (Expanded macro to endif)
Check the verilog-library-directories variable.
I looked in (if not listed, doesn’t exist):
/home/rstevens/elisp/bugs/embeddedIfndef/ip0301_cpuSubsystem.sv

If you search for "///" you will find two lines that you can comment out to get AUTOs to recompute successfully.

I included 2 lower level files that you will need to successfully recompute AUTOs.

Thanks,
Ray Stevens
@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-28T11:03:32Z

For now move the ifndef inside the #( that is:

     #(
 `ifndef SYNTHESIS
       .FILENAME (`CPU_ROMFILE)
 `endif
      )

Verilog-mode has limited tolerance for ifdefs, but this case should have worked, I'll see if this can be easily fixed.

@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Ray Stevens
Original Date: 2019-05-28T14:13:18Z

Thanks for the workaround! (and the very fast response).

@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-28T23:47:00Z

I don't see an obvious real fix, generally verilog-mode ignores most ifdefs and the parsing to handle this otherwise is leading to a mess, so we'll stick with the workaround as how it has to work...

@veripoolbot
Copy link
Collaborator Author

Original Redmine Comment
Author Name: Ray Stevens
Original Date: 2019-05-29T00:38:52Z

OK, thanks for looking into this.

  • Ray

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@wsnyder wsnyder

Labels
autos wontfix
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@wsnyder @veripoolbot