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Issue #1449

deferred assertion support

Added by Charles Eddleston about 2 months ago. Updated about 1 month ago.

Status:
Closed
Priority:
Low
Assignee:
Category:
Unsupported
% Done:

0%


Description

System verilog deferred assertions are treated as syntax errors: http://systemverilog.us/vf/deferred_assertion.pdf

History

#1 Updated by Charles Eddleston about 2 months ago

Error message: syntax error, unexpected final, expecting '(' or property

code: assert final ( !intf_data_in_64_4.tlast ) else begin $error( "[RTL-ASSERT] %0t: %m unexpected TLAST (DATA)", $time );

#2 Updated by Wilson Snyder about 2 months ago

  • Category set to Unsupported
  • Status changed from New to Feature

Seems straight forward to add this. Might you be willing to attempt a patch, or at least a self-checking test checked against another simulator in verilator's test_regress format? Thanks

#3 Updated by Charles Eddleston about 2 months ago

Yeah, I'm not the best with linux, but given instructions, I would be happy to apply the patch and test it out. I'm using ventilator for LINT checks, we use VCS for simulation...so my testing would just be ensuring that both assert #0 and assert final are no longer flagged in LINT.

#4 Updated by Wilson Snyder about 2 months ago

I mean might you be able to come up with a patch that fixes the sources yourself, and/or provide a test_regress style verilog file?

#5 Updated by Wilson Snyder about 2 months ago

  • Status changed from Feature to Resolved
  • Assignee set to Wilson Snyder

Realized all that was needed was parser code pulled from Verilog-Perl.

Fixed in git towards 4.016.

#6 Updated by Wilson Snyder about 1 month ago

  • Status changed from Resolved to Closed

In 4.016.

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