deferred assertion support
System verilog deferred assertions are treated as syntax errors: http://systemverilog.us/vf/deferred_assertion.pdf
#3 Updated by Charles Eddleston about 2 months ago
Yeah, I'm not the best with linux, but given instructions, I would be happy to apply the patch and test it out. I'm using ventilator for LINT checks, we use VCS for simulation...so my testing would just be ensuring that both assert #0 and assert final are no longer flagged in LINT.
Also available in: Atom