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deferred assertion support #1449
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Original Redmine Comment Error message: code: |
Original Redmine Comment Seems straight forward to add this. Might you be willing to attempt a patch, or at least a self-checking test checked against another simulator in verilator's test_regress format? Thanks |
Original Redmine Comment Yeah, I'm not the best with linux, but given instructions, I would be happy to apply the patch and test it out. I'm using ventilator for LINT checks, we use VCS for simulation...so my testing would just be ensuring that both assert #0 and assert final are no longer flagged in LINT. |
Original Redmine Comment I mean might you be able to come up with a patch that fixes the sources yourself, and/or provide a test_regress style verilog file? |
Original Redmine Comment Realized all that was needed was parser code pulled from Verilog-Perl. Fixed in git towards 4.016. |
Original Redmine Comment In 4.016. |
Author Name: Charles Eddleston
Original Redmine Issue: 1449 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
System verilog deferred assertions are treated as syntax errors:
http://systemverilog.us/vf/deferred_assertion.pdf
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