AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
Thanks for the super-quick answer to my last question!
I have a signal like this: logic [7:0] sig_a ;
sig_a comes from one instance of module xx and sig_a1 from the other instance.
sig_a is the input of module yy.
When I expand autos, I get this under /*AUTOLOGIC*/
logic  [7:0] sig_a; // From inst_xx_0
If it's the other direction, it works fine, but it looks like AUTO prioritizes outputs of modules and gets confused. How can I fix this without manually declaring all of these signals?
#1 Updated by Wilson Snyder 8 months ago
- Category set to Autos
- Status changed from New to WillNotFix
Verilog-mode doesn't figure out how to deal with 2-D and up structures, it just assumes the first output is what you want. The combining code is already complicated so is unlikely to get reworked to improve this case, so you'll need to declare it manually.
#2 Updated by David Rogoff 3 months ago
Wilson, I understand you not wanting to fix this but I keep hitting this issue on huge upper-level integration modules - exactly where AUTOs are great. Have you considered making a paid version of verilog-mode to give you and other developers incentive to do some of the more difficult fixes? After years and years of relying on your code (and emacs) I'm starting to look at eclipse with plugins like DVT (which is certainly not free!).
#3 Updated by Wilson Snyder 3 months ago
- Subject changed from Question: AUTOLOGIC/AUTOINST for unpacked array signal input to submodule to AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
- Status changed from WillNotFix to Feature
If you can provide some examples I'll take a look if there's some straightforward cases I can cover (gratis). Please include a reasonable number of cases in a file along with how you think they should be properly combined, including some cases that shouldn't combine. Note presently all the following are different internally so each of these need to be tested against whatever combine permutations:
reg [x:y] packed; reg [x:y][x:y] packed2d; reg unpacked [x:y]; reg unpacked2d [x:y][x:y]; reg [x:y] packedunpacked [x:y]; reg [x:y][x:y] unpacked2d [x:y][x:y];
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