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Issue #1454

Support for loop index into generated arrays

Added by X Yyy 3 months ago. Updated 3 months ago.

Status:
Feature
Priority:
Normal
Assignee:
-
Category:
Unsupported
% Done:

0%


Description

module test(input clk,
            input rst
            );

   generate genvar idx;
      for (idx = 0; idx < 10; idx = idx + 1) begin : prefix
         reg [7:0] r;
      end
   endgenerate

   integer         idx1;

   always @(posedge clk)
     if (~rst) begin
        for (idx1 = 0; idx1 < 10; idx1 = idx1 + 1) begin
           prefix[idx1].r <= 0;
        end
     end

endmodule
For the example above, Verilator fails with the following messages:
%Error: vtst.v:16: Expecting expression to be constant, but variable isn't const: idx1
%Error: vtst.v:16: Could not expand constant selection inside dotted reference: idx1
%Error: vtst.v:16: Can't find definition of 'r' in dotted signal: prefix__BRA__??__KET__.r
%Error:      Known scopes under 'r': <no cells found>
%Error: Exiting due to 3 error(s)

Looks like constant elaboration is attempted before the for loop is unrolled. Interestingly, Icarus fails in a very similar way here. Yosys handles this module correctly though, as well as Xilinx and Altera tools.

History

#1 Updated by Wilson Snyder 3 months ago

  • Subject changed from Incorrect handling of a for loop index to Support for loop index into generated arrays
  • Category set to Unsupported
  • Status changed from New to Feature

Verilator doesn't presently support runtime indexing into cells or named blocks. It does support generated indexing. To work around this, change your for loop to be a generate loop.

 for (idx1 = 0; idx1 < 10; idx1 = idx1 + 1) begin
    always @(posedge clk)
     if (~rst) begin
           prefix[idx1].r <= 0;
        end
    end

#2 Updated by X Yyy 3 months ago

Ok, then the issue is even deeper - why the synthesisable (i.e., constant-bound) behavioural for loops in Verilator are not generated (i.e., not expanded in compilation time), to match the semantics of the synthesised subset of Verilog? What's the reason for keeping them as runtime loops?

#3 Updated by Wilson Snyder 3 months ago

Verilator will unroll both kinds of loops. Generate loops are unrolled at a different stage, elaboration, which is a requirement of the language.

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