Author Name: Paul Donahue
Original Redmine Issue: 1457 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Clocking blocks seem to indent appropriately with verilog-batch-indent but default clocking blocks (IEEE 1800-2017 section 14.12) don't.

Here's what I'm using:
$ emacs --batch --no-init-file --no-site-file -l verilog-mode.el -f verilog-version
Using verilog-mode version 2019-05-06-28bee25-vpo
$ emacs --version
GNU Emacs 25.3.1
Copyright (C) 2017 Free Software Foundation, Inc.
GNU Emacs comes with ABSOLUTELY NO WARRANTY.
You may redistribute copies of GNU Emacs
under the terms of the GNU General Public License.
For more information about these matters, see the file named COPYING.

Here's the before and after of the simplest default clocking block:
$ cat ~/foo.sv
module top;
default clocking @(posedge clk);
endclocking
endmodule
$ emacs --batch --no-init-file --no-site-file -l verilog-mode.el ~/foo.sv -f verilog-batch-indent
Processing /home/pdonahue/foo.sv
Indenting region...
Indenting region...done
$ cat ~/foo.sv
module top;
default clocking @(posedge clk);
endclocking
endmodule

The beginning of the block was correctly moved from 2 to 3 spaces of indentation. The endclocking doesn't align with it, though.

Thanks,

-Paul