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signal_decl not called for definitions in port list #146

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veripoolbot opened this issue May 9, 2007 · 0 comments
Closed

signal_decl not called for definitions in port list #146

veripoolbot opened this issue May 9, 2007 · 0 comments
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Author Name: Mark Nodine
Original Redmine Issue: 146 from https://www.veripool.org
Original Date: 2007-05-09
Original Assignee: Wilson Snyder (@wsnyder)


This bug was cloned from Perl-RT, rt27045.

Email addresses have have been truncated.

Id: 	27045
Status: 	resolved
Left: 	0 min
Queue: 	Verilog-Perl
Owner: 	Nobody
Requestors: 	NODINE <nodine@>

Severity: 	Normal
Broken in: 	2.373
Fixed in: 	3.000
X Attachments
port-test7.v

     * Wed May 09 17:22:26 2007 (781b) by NODINE

Wed May 09 17:22:26 2007 NODINE - Ticket created

Subject: 	signal_decl not called for definitions in port list

None of the signals for module "ansireg" in the attached file have
signal_decl called for them by Verilog::SigParser. They are defined in
the module statement itself:

module ansireg(input clk, reset, input@d, output reg [7:0] q );

Subject: 	port-test7.v

[application/tkgate 781b]
Message body not shown because it is too large or is not plain text.

Wed Jun 13 12:32:38 2007 WSNYDER - Fixed in 3.000 added

Wed Jun 13 12:32:40 2007 WSNYDER - Status changed from 'new' to 'resolved'

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