Structs as output ports don't work with stub generation recipe
module Foo (input logic Clk, output DutPkg::FullOutput_s FullOutput);
I followed the recipe for generating stubs from https://www.veripool.org/projects/verilog-mode/wiki/Faq#How-do-I-make-a-Stub-moduleHowever, verilog-mode doesn't seem to recognize FullOutput as an output:
module FooStub (/*AUTOARG*/ // Inputs Clk ); /*AUTOINOUTPARAM("Foo")*/ /*AUTOINOUTMODULE("Foo")*/ // Beginning of automatic in/out/inouts (from specific module) input logic Clk; DutPkg::FullOutput_s FullOutput; // End of automatics endmodule : FooStub
I would expect FullOutput to be in the port list and the "output" keyword to appear in the AUTOINOUTMODULE section. In playing around, I found that it seems to work if FullOutput is declared as one of the built-in types but not when it is something else I typedef'ed.
I have attached a tarball with the Foo module, the FooStub module, a Makefile, and the verilog-mode.el I used (which is the latest from last week).
#1 Updated by Wilson Snyder 2 months ago
- Status changed from New to NoFixNeeded
Thanks for the very clear example, this makes it a lot easier.
Unfortunately Verilog-mode needs to know what is a type (as in cases without the :: it might otherwise be an interface). If you add this to Foo.sv and FooStub.sv it works, or equivalently to some startup file.
// Local Variables: // verilog-typedef-regexp: "_s$" // End:
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