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Issue #1461

Structs as output ports don't work with stub generation recipe

Added by Paul Donahue 5 days ago. Updated 5 days ago.

Status:
NoFixNeeded
Priority:
Normal
Assignee:
Category:
Autos
% Done:

0%


Description

I have this port list on a module:
module Foo (input logic Clk,
            output DutPkg::FullOutput_s FullOutput);

I followed the recipe for generating stubs from https://www.veripool.org/projects/verilog-mode/wiki/Faq#How-do-I-make-a-Stub-module

However, verilog-mode doesn't seem to recognize FullOutput as an output:
module FooStub (/*AUTOARG*/
   // Inputs
   Clk
   );
  /*AUTOINOUTPARAM("Foo")*/
  /*AUTOINOUTMODULE("Foo")*/
  // Beginning of automatic in/out/inouts (from specific module)
  input logic        Clk;
  DutPkg::FullOutput_s    FullOutput;
  // End of automatics
endmodule : FooStub

I would expect FullOutput to be in the port list and the "output" keyword to appear in the AUTOINOUTMODULE section. In playing around, I found that it seems to work if FullOutput is declared as one of the built-in types but not when it is something else I typedef'ed.

I have attached a tarball with the Foo module, the FooStub module, a Makefile, and the verilog-mode.el I used (which is the latest from last week).

Thanks,

-Paul

stub.tar.gz (127 KB) Paul Donahue, 06/11/2019 08:51 PM

History

#1 Updated by Wilson Snyder 5 days ago

  • Status changed from New to NoFixNeeded

Thanks for the very clear example, this makes it a lot easier.

Unfortunately Verilog-mode needs to know what is a type (as in cases without the :: it might otherwise be an interface). If you add this to Foo.sv and FooStub.sv it works, or equivalently to some startup file.

// Local Variables: // verilog-typedef-regexp: "_s$" // End:

#2 Updated by Paul Donahue 5 days ago

Thanks for another fast response. I'm sorry to bother you since I see now that this is already documented.

Your suggestion, of course, works great.

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