Project

General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Issue #1463

Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module.

Added by Utkarsh Khanna 7 months ago. Updated 7 months ago.

Status:
WillNotFix
Priority:
Normal
% Done:

0%


Description

Suppose I have a verilog file with modules and lots of sub modules and also with pins inside the submodule. I want to display the whole address of the pin or port input by user

History

#1 Updated by Wilson Snyder 7 months ago

  • Status changed from New to WillNotFix

This is not supported by vhier, and is unlikely to be added in the future, sorry. To do this you'd need to write your own perl program that uses the Verilog::Netlist package.

Also available in: Atom